Binary system adder-subtractor based on enhancement-type LUT (look up table) 5 structure

Abstract

The invention relates to a binary system adder-subtractor, and discloses a binary system adder-subtractor based on an enhancement-type LUT (look up table) 5 structure. According to the invention, the binary system adder-subtractor comprises an enhancement-type 5 input LUT structure, a carry chain structure and a standard xor structure; addition and subtraction logic of two digits is realized for the LUT5 structure by utilizing a LUT 4 with two 3 input share; the port resource utilization ratio achieves 4 / 5; when controllable addition and subtraction logic (with addition and subtraction control signal input) is realized, the port resource utilization ratio even achieves 5 / 5=100%; compared with the existing individual 4 input LUT, one digit addition and subtraction is realized, the port utilization ratio is increased by 30%, and the area utilization ratio is improved greatly. Additionally, the carry chain structure comprises two carry look ahead structures; two carry chain logic delays are lowered from two traditional selectors to delay time of a tristate phase inverter; the digit transmission delay is reduced; and the working frequency of the adder-subtractor is improved.

Description

technical field [0001] The invention relates to a binary adder-subtractor, in particular to a binary adder-subtractor based on an enhanced LUT5 structure. Background technique [0002] In programmable logic devices, random logic functions and sequential logic in user designs are usually implemented by programmable logic cells. For field programmable logic arrays (FPGA), most programmable logic units are internally composed of a certain number of look-up table ("LUT") structures and sequential units (edge-triggered registers or level-type locks) memory), and an N-input lookup table structure is used to implement any N-input combinational logic function, using 2 in the lookup table structure N The storage array of saves the function values ​​corresponding to N inputs. The programmable logic cells are connected together through pre-customized metal wiring and controllable switches (programmable interconnect). [0003] In most designs that need to be implemented by FPGA, a la...

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Problems solved by technology

[0015] However, for example, Xilinx’s existing implementation of addition and subtraction has the problem of low utilization of hardware resources: when using a single LUT4 structure and carry logic to implement addition and subtraction, the programmable logic unit wastes a lot

[0016] Therefore, the inventors of the present invention have found that the number of look-up table structures consumed by the logical function generating part based solely on the look-up table structure when realizing the logic of addition and subtraction is too large, resulting in huge area and increased cost. The interconnection connection carry logic also makes the delay of the large-bit width addition and subtraction logic too large to meet the needs of high-speed design

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