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Base-2 parallel FFT (fast Fourier transformation) processor based on DIF (decimation in frequency) and processing method thereof

A processing method and processor technology, applied in the direction of complex mathematical operations, etc., can solve problems such as insufficient flexibility, and achieve the effect of improving processing speed and system throughput

Inactive Publication Date: 2013-03-06
SHANGHAI BOOM FIBER SENSING TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, use multiple special-purpose chips to form a parallel structure to quickly realize long-sequence FFT, but this method is based on special-purpose chips and has insufficient flexibility.

Method used

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  • Base-2 parallel FFT (fast Fourier transformation) processor based on DIF (decimation in frequency) and processing method thereof
  • Base-2 parallel FFT (fast Fourier transformation) processor based on DIF (decimation in frequency) and processing method thereof
  • Base-2 parallel FFT (fast Fourier transformation) processor based on DIF (decimation in frequency) and processing method thereof

Examples

Experimental program
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Effect test

Embodiment 1

[0027] This embodiment provides a DIF-based radix-2 parallel FFT processor, such as figure 1 As shown, it includes a parallel FFT input operator 1, a twiddle factor module 2 and an FFT processor 3; the parallel FFT input operator 1 includes 2 M Road parallel adder and subtractor 11 and delay unit 12, wherein M is a non-negative integer; the FFT IP core 3 includes 2 M Parallel FFT IP core 31; 2 M Parallel adder and subtractor 11 and 2 M The parallel FFT IP cores 31 are connected one by one; the output sequence of each adder-subtractor 11 is multiplied by the corresponding twiddle factor in the twiddle factor module 2 and input to the corresponding FFT IP core 31 connected to itself.

[0028] The input sequence length of the DIF-based radix-2 parallel FFT processor is K·2 M , where K is a positive integer, and the length of the sequence processed by the FFTIP core 31 is K. The twiddle factor lookup table is stored in the twiddle factor module 2 . The input terminal and / or o...

Embodiment 2

[0035] This embodiment provides a base-2 parallel FFT processor based on DIF, such as figure 2 As shown, the difference between it and Embodiment 1 is: the parallel FFT input operator includes 4-way parallel adder and subtractor, and the FFT processor includes 4-way parallel FFT IP cores; the base-2 parallel FFT processor based on DIF The input sequence is of length N.

[0036] image 3 Shows a standard N=16-point FFT operation flowchart of the decimation by frequency method (DIF), wherein the data flow after the first two stages is clearly divided into four independent units horizontally (such as image 3 Shown by the dotted line in the middle), each unit implements N / 4-point FFT independently, thus forming a four-way parallel structure. Therefore, four N / 4-point FFT units can be used to calculate N-point FFT in parallel, that is, the so-called parallel structure FFT. Then design a specific structure of the arithmetic circuit to handle the first two stages.

[0037] The ...

Embodiment 3

[0087] In this embodiment, in the case of single-way, double-way and four-way parallel, the resources (Resources) consumed by the FFT processor, the clock frequency (Maximum Speed) that can be achieved, the waiting time (Latency), the conversion time ( TransformTime) and system throughput (Throughput) etc., further prove the beneficial effect of the parallel FFT processor proposed by the present invention and its processing method.

[0088] The radix-2 parallel FFT processor based on DIF described in the present invention has been verified on the experimental board DASQ_USB_V1 with Virtex-II serial FPGA XC2V3000. The real sequence with a length of 2048 points is split into four input FPGAs, and the four parallel FFT units use the free FFT IP core that comes with the Xilinx FPGA development tool ISE10.1, which can realize pipeline input and output. An FFT verification result with an input sequence length of N=2048 is shown in Table 1. The input and output data in the table are ...

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Abstract

The invention discloses a base-2 parallel FFT (fast Fourier transformation) processor based on DIF (decimation in frequency) and a processing method thereof. The processor comprises a parallel FFT input arithmetic unit, a twiddle factor module and an FFT processor. The parallel FFT input arithmetic unit comprises 2M parallel adder--subtractors and delay units for achieving time synchronization, wherein M is a nonnegative integer. The FFT processor comprises 2M parallel FFTIP (fast Fourier transform intellectual property) cores. The 2M parallel adder-subtractors are in one-to-one correspondence connection with the 2M parallel FFTIP cores. An output sequence of each adder-subtractor multiplies a corresponding twiddle factor in the twiddle factor module and is input to one FFTIP core in one-to-one correspondence connection with the adder-subtractor. The delay units are disposed at input ends or / and output ends of the adder-subtractors in the FFT input arithmetic unit. The base-2 parallel FFT processor based on DIF splits long sequences into short sequences, FFT of the short sequences is achieved by the FFTIP cores, and accordingly processing speed and system throughput are increased linearly.

Description

technical field [0001] The invention belongs to the technical field of signal and information processing, and relates to an FFT processor, in particular to a DIF-based radix-2 parallel FFT processor and a processing method thereof. Background technique [0002] FFT has a very wide range of applications in the field of digital signal processing, but the long-sequence FFT has a large amount of calculation and is difficult to implement. With the development of high-speed devices, there are many researches on how to quickly realize long-sequence FFT, and various realization methods have emerged one after another. For example, multiple special-purpose chips are used to form a parallel structure to quickly realize long-sequence FFT, but this method is based on special-purpose chips and has insufficient flexibility. In recent years, FPGA devices have developed rapidly, and its programmable reconfiguration features make it more and more widely used in many fields. Xilinx's Virtex-...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/14
Inventor 黄正
Owner SHANGHAI BOOM FIBER SENSING TECH
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