The invention provides a full-
adder arithmetic element circuit. The full-
adder arithmetic element circuit comprises a first-order gate circuit, a second-order gate circuit and a third-order gate circuit, wherein the first-order gate circuit comprises an
NOR gate 1, an
NOR gate 2, an
NOR gate 3 and an NOR gate 4, the inputs of the four NOR gates are respectively as follows: (A, B), (B, Cin), (A, Cin), and (A, B, Cin), wherein the A, B and Cin are three one-bit binary input signals, and the outputs of the four NOR gates are respectively as follows: Y11, Y12, Y13, and Y14; the second-order gate circuit comprises an NOR gate 5, an NOR gate 6, an NOR gate 7 and an NOR gate 8, the inputs of the four NOR gates are respectively as follows: (A, Y11, Y13), (B, Y11, Y12), (Cin, Y12, Y13), and (Y11, Y12, Y13), and the outputs of the four NOR gates are respectively as follows: Y21, Y22, Y23, and Cout; and the third-order gate circuit comprises an NOR gate 9, the input of the NOR gate 9 is (Y21, Y22, Y23, Y14), and the output of the NOR gate 9 is S.