The invention discloses an insulated gate bipolar transistor, and the transistor comprises an N- base region, a P+ base region, an N+ emitter region, an emitter region, a gate oxide layer, a gate electrode, an N-type buffering layer, a P+ collector region, a thin silicon dioxide layer, an N-type polycrystalline silicon region, and a collector electrode. The transistor is characterized in that the P+ base region, the N+ emitter region, the emitter region, the gate oxide layer and the gate electrode are located at one side of the N- base region; the N-type buffering layer, the P+ collector region, the thin silicon dioxide layer, the N-type polycrystalline silicon region and the collector electrode are located at the other side; the thin silicon dioxide layer and the N-type polycrystalline silicon region are sequentially stacked through the P+ collector region to form a polycrystalline silicon emitter region which does not cover the P+ collector region completely. The N-type buffering layer, the P+ collector region and the polycrystalline silicon emitter region form a quick switching polycrystalline silicon emitter NPN-type triode, thereby forming a non-balance carrier extraction quick channel during the switching-off of the transistor, and facilitating the quick switching of the transistor.