31results about How to "Reduce signal transmission delay" patented technology

The invention provides a method and device for multimedia group calling business in the mobile network. The voice group calling is established by the circuit exchange and the data combination can be established by the branch exchange.

The invention belongs to the field of electronic ceramic materials, and provides a low thermal expansion cordierite-based glass-ceramic material and a preparation method thereof, which are used for ultra-large-scale integrated circuit packaging. The glass-ceramic material of the present invention is composed according to the mass percentage: MgO is 15-19wt%, Al 2 o 3 26~30wt%, SiO 2 46~50wt%, ZrO 2 2~6wt%, B 2 o 3 1~5wt%, K 2 O is 1 ~ 3wt%; by introducing K 2 O as modifier, ZrO 2 As a crystal nucleating agent, B 2 o 3 As a fever reducer, it inhibits a part (MgAl 2 Si 3 o 10 ) 0.6 phase inversion to Mg 2 al 4 Si 5 o 18 phase, thereby adjusting the coefficient of thermal expansion towards the Si chip (3.5×10 ‑6 / ℃), and at 2.5~3.5×10 ‑6 / °C adjustable, good thermal stability; at the same time, the bending strength can reach 150-200MPa, the Young's modulus can reach 80-95GPa, the dielectric constant is 5-6 (@1MHz), and the dielectric loss is 0.5-1× 10 ‑3 (@1MHz), which can increase the signal transmission speed and greatly reduce power consumption; in summary, the low thermal expansion cordierite-based glass-ceramic material of the present invention is suitable for VLSI packaging, which can significantly reduce signal transmission delay and power consumption , well matched with silicon chips.

The connector has terminals (20) i.e. signal terminals, arranged in an insulated housing (10), where the housing has a fixed part and an air-opening part. An earth contact (30) is provided for producing earth shielding and separated from the housing, where the earth contact passes through the terminals. An opening (31) is provided in the earth contact and formed corresponding to the fixed part of the housing. The fixed part has a reinforcing rib, and a projecting partial area (11) is formed at perforation areas of the housing, where the housing has a flat plate assembly.

The invention discloses a novel method for winding compensation in a via through hole. In design of a printed circuit board (PCB) card, winding compensation is performed by vertical wiring on a hole wall of the via through hole vertically penetrating through a PCB. The via through hole vertically penetrating through the PCB is utilized, signal winding compensation is performed in the via through hole, signal transmission delay on the PCB is reduced, meanwhile, the space utilization of a PCB panel is improved, and the board card performance is optimized.

The invention discloses a thin film transistor array substrate and manufacturing and repairing methods of the thin film transistor array substrate which comprises a plurality of grid scanning lines extending along a first direction and a plurality of data lines extending along a second direction. The grid scanning lines and the data lines intersect with each other and form a pixel region, in which a thin film transistor and a pixel electrode are arranged. Metal pattern formed above the grid scanning lines or below the data lines are separated from the data lines metal layer pattern and the grid scanning lines metal layer pattern. The invention can repair the broken-circuit of the data lines and the grid scanning lines in the pixel section without additional fabrication procedure of the existing array substrate and with simple and convenient repairing.

The invention provides a multilayer interconnection packaging structure of an embedded microwave multi chip with a silicon chip as a substrate and a manufacturing method. The invention is characterized by utilizing the low-cost silicone chip as the chip embedded substrate and using wire bonding and ball mounting technology to prepare gold bumps, realizing short-distance interconnection between microwave chips, using a low-k liquid or colloidal polymer as a dielectric layer, realizing the multilayer interconnection structure of a metal / organic polymer by combining wafer level processing technics such as photoetching, electroplating, chemical mechanical polishing and the like and realizing system integration of active and passive devices. The whole packaging structure has higher packaging integration and lower high-frequency transmission loss. The structure can effectively integrate varied function device units, reduce the interconnection loss among the devices and improve the properties of the whole module while improving the density and integration of packaging and reducing the cost of packaging.

The invention discloses a multi-chip package, comprising: a substrate, which is provided with a substrate circuit and has a first surface and a second surface opposite to the first surface, wherein a central groove is formed on the first surface, and a second surface is formed on the second surface. The surface is symmetrically formed with at least one pair of second surface grooves with respect to the center of the central groove; the chip set, each chip is arranged in the central groove and each second surface groove in equal numbers, and is matched with the substrate circuit an electrical connection; and an encapsulation layer, encapsulating the chipset on the substrate, thereby protecting each chip. According to the present invention, the problems of signal transmission delay and signal asynchrony during multi-chip packaging can be effectively reduced.