A low-voltage high-speed inductive load drive circuit

Abstract

The invention provides a low-voltage high-speed inductive loading driving circuit. High-speed low-voltage high-amplitude outputting can be guaranteed, a zero-passage interval of high-speed data of a bus can also be effectively improved, the communication requirement of a 4M 1553 bus is met, and the communication reliability of a system is improved. The low-voltage high-speed inductive loading driving circuit comprises a driving logic module, pre-driving modules and negative-feedback-slope control modules; a bus signal BUS is output by one pre-driving module and one negative-feedback-slope control module which are sequentially connected with one output end of the driving logic module, and a bus differential signal XBUS is output by another pre-driving module and another negative-feedback-slope control module which are sequentially connected with another output end of the driving logic module; the negative-feedback-slope control modules are used for controlling the positive edge and the negative edge of the bus output signal, and it is prevented that the output signal is subjected to zero returning to be vibrated; the pre-driving modules are used for driving the negative-feedback-slope control modules.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a low-voltage high-speed inductive load drive circuit. Background technique [0002] The current structure of the 1M 1553 bus low-voltage drive circuit is as follows: figure 1 As shown, including the drive logic module and the slope control circuit module. The drive logic module is composed of a plurality of NOT gates, NAND gates and NOR gates, which mainly realize signal shaping, differential signal output of TX and XTX, in-phase signal shielding, enable signal control, and realize the logic control of the drive circuit. The ramp control circuit structure is as figure 2 As shown, the charging tube PMOS transistor MP1, the discharging tube NMOS transistor MN1, the RC charging current limiting resistor R2, the RC discharging current limiting resistors R1, R2, the RC time constant capacitor C1 is set, and the bus drives the high voltage PMOS transistor MP2. Among th...

AI Technical Summary

Problems solved by technology

If the circuit needs to drive the 4M 1553 bus, since the circuit uses RC charging and discharging, under high-speed conditions, the gate-source voltage of the high-voltage PMOS transistor is about 1V lower than VDD when the MP2 gate capacitance discharges, causing the output amplitude of the drive circuit to decrease; in addition, the 4M When the 1553 bus communicates normally, the data cycle is 125ns, 250ns, 375ns, 500ns. Since the RC charging and discharging circuit is used to control the slope of the driving signal, the gate-source voltage of the high-voltage PMOS transistor MP2 has a large difference when the low-frequency data and high-frequency data are driven. , when low-frequency data transitions to high-frequency data, the zero-crossing interval parameters of high-frequency data are out of tolerance, resulting in the failure of normal communication in the 4M 1553 bus system

Images