Set-associative cache memory having variable time decay rewriting algorithm

Abstract

A set-associative structure replacement algorithm is particularly beneficial for irregular set-associative structures which may be affected by different access patterns, and different associativities available to be replaced on any given access. According to certain aspects, methods and apparatuses implement a novel decay replacement algorithm that is particularly beneficial for irregular set-associative structures. An embodiment apparatus includes set-associative structures having decay information stored therein, as well as update / replacement logic to implement replacement algorithms for translation lookup buffers (TLBS) and caches that vary in the number of associativities; have unbalanced associativity sizes, e.g., associativities can have different numbers of indices; and can have varying replacement criteria. The implementation apparatuses and methods provide good performance, on the level of LRU, random and clock algorithms; and is efficient and scalable.

Description

1. Field of the InventionThe present invention is directed to microprocessor architectures. More particularly, the invention is directed to TLBs and cache memories for speeding processor access to main memory in microprocessor systems. Even more particularly, the invention is directed to methods and apparatuses for implementing novel refill policies for multi-way set associative caches and TLBs.2. Background of the Related ArtCaches and Translation Lookaside Buffers (TLBs) are ubiquitous in microprocessor design. For general information on such microprocessor structures, see J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitive Approach (1996), Chapter 5.Generally, the speed at which a microprocessor (e.g. a CPU) operates depends on the rate at which instructions and operands are transferred between memory and the CPU. As shown in FIG. 1, a cache 110 is a relatively small random access memory (RAM) used to store a copy of memory data in anticipation of future use b...

AI Technical Summary

Problems solved by technology

The replacement algorithm can have adverse affects on processor performance by making bad choices for replacement.

For instance, replacing data which will be used soon is worse than replacing data that will not be used again, because the first choice would cause another "miss," whereas the second choice would not.

Although set-associative memories with heterogenous ways can provide value over traditional set-associative memories with homogenous ways, replacement algorithms that work on a "set" basis either no longer work, are inefficient, or are difficult to implement.

In particular, current replacement algorithms are ill suited towards, or inefficient at one or more of the following: (1) handling heterogenous ways that can even allow the indexing of ways to change at run-time (i.e. Is the way configured to translate 4 KB or 4 MB pages); (2) handling way replacement criteria (i.e. Is the way configured to translate 4 KB or 4 MB pages); and (3) handling associative structures that do not have 2**N ways.

Most LRU implementations have similar issues, since they implement state that tracks LRU on a set basis.

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