62 results about "Quad Flat No-leads package" patented technology

A thermally enhanced quad flat non-lead package of semiconductor comprises a chip a plurality of leads, and a molding compound. The chip has its active surface bonded to the top surface of the die pad, and the area of the die pad is smaller than that of the chip in order to expose the bonding pads on the active surface of the chip. The leads are disposed at the periphery of the die pad wherein the bottom surface of the lead has a stepped structure with a relatively thin portion to form a wire-bonding protruded zone. A plurality of bonding wires is used to electrically connect the wire-bonding protruded zone of the leads to the bonding pads of the chip. The molding compound encapsulates the chip, bonding wires, the die pad, and a portion of the surface of the leads, but exposes the bottom surface of the die pad. In this way, the encapsulating process makes the side surface of the lead, and the portion excluding the wire-bonding protruded zone of the bottom surface of the lead exposed in order to make the lead become the external connecting points of the package structure.

An integrated power device module having a leadframe structure with first and second spaced pads and one or more common source-drain leads located between said first and second pads, first and second transistors flip chip attached respectively to said first and second pads, wherein the source of said second transistor is electrically connected to said one or more common source-drain leads, and a first clip attached to the drain of said first transistor and electrically connected to said one or more common source-drain leads. In another embodiment a partially encapsulated power quad flat no-lead package having an exposed top thermal drain clip which is substantially perpendicular to said with a folded stud exposed top thermal drain clip, and an exposed thermal source pad.

A packaged device adapter assembly for use with high density integrated circuit packages, e.g., micro lead frame packages, micro lead chip carriers, quad flat no lead packages, and micro ball grid array packages, etc., includes an alignment structure for aligning a packaged device therein.

The present invention provides a QFN package structure, comprising a chip carrier and at least a chip. The chip is disposed on the top surface of the chip carrier, while the back surface of the chip carrier includes a plurality of flat no-lead conductive leads as I/O pads of the chip carrier for the external circuitry. A plurality of pads, corresponding to bonding pads of the chip, is disposed on the top surface of the chip carrier. The aforementioned package structure can employ wiring bonding technology, flip chip technology or surface mount technology to attach the chip to the chip carrier.

A quad flat non-leaded (QFN) package structure with an electromagnetic interference (EMI) shielding function is proposed, including: a lead frame having a die pad, a plurality of supporting portions connecting to the die pad and a plurality of leads disposed around the periphery of the die pad without connecting to the die pad; a chip mounted on the die pad; bonding wires electrically connecting the chip and the leads; an encapsulant for encapsulating the chip, the bonding wires and the lead frame and exposing the side and bottom surfaces of the leads and the bottom surface of the die pad; and a shielding film disposed on the top and side surfaces of the encapsulant and electrically connecting to the supporting portions for shielding from EMI. A method of fabricating the package structure as described above is further proposed.

A manufacturing method for a Flip Chip Quad Flat Non-leaded package structure is provided. A lead frame having a plurality of leads is provided at first in the manufacturing method. A dielectric layer is formed on the lead frame and exposes a top surface and a bottom surface of the leads. A redistribution layer including a plurality of pads and a plurality of conductive lines connected the pads and the top surface of the leads is formed on the dielectric layer. A solder resist layer is formed to cover the redistribution layer, the dielectric layer and the leads, and expose the surface of the pads. An adhesive layer is formed on the solder resist layer. A chip having a plurality of bumps is provided. The chip is adhered on the solder resist layer with the adhesive layer and each bump is electrically connected with one of the pads.

The invention relates to a novel LED (Light Emitting Diode) packaging piece based on DFN (Double Flat No-lead package) and QFN (Quad Flat No-lead Package), and a manufacturing method of the packaging piece, belonging to the technical field of automatic electronic information components. The packaging piece comprises a lead frame carrier, a glue chip, an IC (Integrated Circuit) chip, a bonding line and a plastic packaging body, wherein the glue chip is fixed on the lead frame carrier; the IC chip is fixed on the glue chip; the PAD bonding line of the IC chip is connected with the lead frame carrier so as to form a current and signal channel of a circuit; and the plastic packaging body surrounds the lead frame carrier, the glue chip, the IC chip, the PAD on the IC chip and the bonding line connected with the lead frame carrier so as to form the overall circuit. The size of a product can be reduced effectively; and the packaging piece belongs to the high density packaging that the carrier is exposed, so that the cost is reduced, the application range of the product is expanded, and the packaging reliability is improved.

The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package. The quad flat no lead package is manufactured through the following steps of: thinning and scribing a wafer; manufacturing a lead frame; loading the chip; performing pressure welding and plastic packaging; performing post-curing; printing; electroplating; separating the leads; separating a product; and testing/braiding. According to the package, the problems of few leads, long welding wire, high welding cost and limited frequency application during single-face packaging of the existing normal quad flat no lead package are solved.

A quad flat non-leaded package structure including a die pad, a plurality of leads, a chip, and a molding compound is provided. The die pad has a top surface and an opposite bottom surface, and the leads are disposed around the die pad. A concave portion is disposed at the end of each leads. The chip is disposed on the top surface of the die pad and is electrically connected to the leads. The molding compound encapsulates the chip, a portion of the leads and the die pad, and fills the gaps between the leads.

The invention discloses a method for maintaining an AQFN (Advanced Quad Flat No-Lead Package) mobile phone motherboard and a maintenance table. The method comprises the following steps of: 1, fixing the motherboard to be maintained, an upper air gun and a lower air gun on respective fixing tables which are adjusted in place respectively; 2, setting proper temperature and air speed of the upper air gun and the lower air gun respectively; 3, simultaneously starting the upper air gun and the lower air gun for heating and unsoldering; 4, cleaning a bonding pad; 5, smoothly coating a solder wire of the bonding pad; 6, performing chip balling; and 7, simultaneously starting the upper air gun and the lower air gun for heating and reflow soldering. The maintenance table comprises a pedestal 1, a stand 2, a lower air gun fixing table 3, a motherboard fixing table 4 and an upper air gun fixing table 5, wherein the stand 2 is fixed at a middle position of the pedestal 1; the lower air gun fixing table, the motherboard fixing table and the upper air gun fixing table are sleeved on the stand respectively; and each fixing table is provided with an adjusting, locking and fixing structure opposite to the stand. The maintenance method and the maintenance table have the advantages of high maintenance efficiency and low reject ratio; and the maintenance table is low in cost, has small occupied area and is suitable to be arranged on a mobile phone production line.

The invention provides a surface mount technology process for an advanced quad flat no-lead package process and a stencil used therewith. The surface mount technology process for an advanced quad flat no-lead package includes providing a printed circuit board. A stencil with first openings is mounted over the printed circuit board. A solder paste is printed passing the first openings to form first solder paste patterns. The stencil is taken off. A component placement process is performed to place the advanced quad flat no-lead package comprising a die pad on the printed circuit board, wherein the first solder paste patterns contact a lower surface of the die pad, and an area ratio of the first openings to the lower surface of the die pad is between 1:2 and 1:10. A reflow process is performed to melt the first solder paste patterns to surround a sidewall of the die pad.

Provided are an area array quad flat no lead package (AAQFN) package body package in package (PiP) piece with solder balls and a production method. The AAQFN package body PiP piece with the solder balls comprises a bare copper frame with multiple pits, an IC chip with salient points is mounted on the front face of the bare copper frame inversely, lower packing is filled between the salient points of the chip and the pits, a first groove is formed in the bare copper frame, two leads which are not connected with each other are formed on the two sides of the first groove, plastic package is carried out on the IC chips with salient points, connecting layers connected with the corresponding leads are arranged on the lower faces of the leads, the solder balls are arranged on the surfaces of all the connecting layers, two layers of IC chips are attached to a first plastic package body, the two layers of IC chips are connected through bonding wires and are connected with the leads through bonding wires respectively, and secondary plastic package is carried out. Through the working procedures of wafer thinning and dicing, bare copper frame processing, upper chip inverse mounting, passivation layer coating and etching, chemical sedimentation and the like, the AAQFN package body PiP piece with the solder balls is prepared. The PiP piece product is smaller in size, higher in packaging density, more in function and capable of replacing parts of BGA PiP and CSP PiP.

The invention provides a production method of resin-based diamond cutting chip for cutting QFN (Quad Flat No-lead Package) substrates. The resin-based cutting chip is produced by combining superfine resin powder, a superfine inorganic filler, superfine metal powder and Ni-plated diamond according to a certain ratio, wherein the content of the superfine resin powder is 50wt%; the content of the superfine inorganic filler is 30wt%; the content of the superfine metal powder is 20wt%; the content of the diamond is 18.75-58vol%. The production method of the resin-based diamond cutting chip comprises the following steps: firstly proportioning the powder and then uniformly mixing the powder by using a hot-press forming device, then pressing the mixture into a cutting chip blank under certain hot-press forming process conditions, curing the cutting chip blank under certain curing process conditions and finally precisely grinding and machining the cured cutting chip blank to obtain the resin-based diamond cutting chip which meets the required specification and has thickness of 0.10-0.20mm. Through the production method of resin-based diamond cutting chip for cutting QFN substrates, the strength, the rigidity, the heat resistance and the abrasion resistance of the cutting chip can be effectively improved; the service life of the cutting chip can be effectively prolonged; compared with cutting chips produced by conventional components and processes for cutting the QFN substrates with the thickness of 0.7-1.1mm, the service life of the cutting chip is prolonged by 100-120%.

The invention relates to a quad flat no-lead package lead frame structure. The quad flat no-lead package lead frame structure comprises a plurality of bearing units in matrix arrangement and middle glutens (3) arranged between and used for fixing the bearing units, wherein each bearing unit comprises a chip carrier (1) and a pin array (2) arranged at the periphery of the chip carrier; each middle gluten (3) is connected between the pin arrays (2) of two adjacent bearing units of the bearing units; a half-etched groove (4) is formed in the back, close to the corresponding middle gluten (3) , of each of the pin arrays (2). According to the quad flat no-lead package lead frame structure, as the half-etched grooves are formed in the root parts of pins, during applying of solder paste to a PCB, the solder paste can more successfully climb to the side edges of the pins through the siphonic effect, and accordingly, combination of the pins and the PCB is enhanced; as the half-etched grooves are formed in the root parts of the pins, the thickness of metal at the root parts of the pins is reduced, accordingly, tool abrasion is reduced and the quad flat no-lead cutting efficiency is greatly improved.

An array QFN package (10) includes a first semiconductor package (12) and a lead frame (14) having a plurality of leads (16). A first IC die (22) is attached on a first side to the first semiconductor package (12) and is electrically connected to the leads (16) of the lead frame (14). A mold compound (30) encapsulates the first IC die (22), a portion of the first semiconductor package (12) and a portion of the leads (16) such that a plurality of I/O terminals (32) on the semiconductor package (10) is exposed.

In a method of manufacturing a lead frame for use in a leadless package such as a quad flat non-leaded package (QFN), a base frame is first formed which includes a region for resin-molding a plurality of semiconductor elements to be mounted on one surface of the base frame, the region being partitioned into land shapes, and in which a die-pad portion and lead portions around the die-pad portion are defined severally for the individual semiconductor elements to be mounted in each of the partitioned regions for resin-molding. Next, an adhesive tape is attached to the other surface of the base frame, and subsequently a cut portion is provided at a portion corresponding to a region between two adjacent partitioned regions for resin-molding, of the adhesive tape.

The invention provides a down folding type runner removal device for an automated packaging system. The down folding type runner removal device comprises a concave die mechanism and a convex die mechanism, wherein the concave die mechanism comprises two first frames, two second frames, two concave dies, two first concave die locking blocks, two second concave die locking blocks, a fixed plate anda plurality of springs; the convex die mechanism comprises a main frame and CULL adsorption mechanism and two convex die folding mechanisms; the main frame and CULL adsorption mechanism comprises fourconvex die locking blocks, two internal storage limiting blocks, a substrate, two CULL linear bearings, two punching plates, a CULL pressing plate and a plurality of suction cups; and each convex diefolding mechanism comprises a pressing plate, a linear guide rail, an intermediate connecting plate and a bent plate. The down folding type runner removal device for the automated packaging system issimple and reliable in structure, can realize the packaging mode that a runner is on an upper die, and achieves runner removal technological processes of high-end package such as Quad Flat No-lead Package (QFN) and Ball Grid Array (BGA) of integrated circuits.

The invention provides a method for manufacturing a quad flat no-lead package, comprising the following steps: providing a motherboard; forming a mold layer on the upper surface of the motherboard; forming a through hole penetrating to the upper surface of the motherboard on the surface of the mold layer, The opening area of ​​the through hole close to the upper surface of the motherboard is smaller than the opening area of ​​the other side; the chip tray and the chip electrode are formed in the through hole; the chip is fixed on the surface of the chip tray; between the chip and the chip electrode forming electrical leads between them; forming a plastic package on the upper surface of the motherboard; removing the motherboard to expose the chip tray and chip electrodes embedded in the plastic package.

The invention belongs to the technical field of package, and relates to QFN (quad flat no-lead package) adhesive removal and softening integrated soak solution. The QFN adhesive removal and softeningintegrated soak solution in a formula comprises 0.5-5 wt% of block polyether surfactants, 20-40 wt% of organic alkali, 0.1-5 wt% of inorganic alkali, 30-50 wt% of organic solvents, 20-30 wt% of alcohol ether dispersing agents, 0.01-0.05 wt% of metal corrosion inhibitors and the balance deionized water. The block polyether surfactants comprise one or two types of propylene glycol polyoxyethylene polypropylene oxide block polymers and allyl polyoxyethylene polypropylene oxide methyl ether. The QFN adhesive removal and softening integrated soak solution has the advantages that the QFN adhesive removal and softening integrated soak solution is excellent in adhesive removal and softening ability and easy to clean, integral technologies only take the total time of 25-45 min, processes can be shortened to be 1/4 of the original processes, and accordingly the productivity can be greatly improved; the solution soak time is only 1/4 of the original solution soak time, and plastic package bodiescan be prevented from being damaged.

A thin quad flat no-lead (QFN) package method comprises the following steps of: adopting a first coating substance (plastic package material) to be coated on a first surface (the back) of a wafer and form a continuous covering layer; cutting the wafer into a plurality of discrete semiconductor crystalline grains, each of which has the covering layer cut down from the continuous covering layer on the surface; mounting the covering layers of the plurality of discrete semiconductor crystalline grains on the surface of an adhesive film on a frame; after wire welding (lead bonding), adopting a second coating substance (plastic package material) to be coated on an exposed surface above an adhesive surface, and the second coating substance wraps together the semiconductor crystalline grains mounted on the adhesive surface to form a whole block of plastic package body; and cutting the whole block of plastic package body and obtaining a plurality of discrete completely packaged semiconductor crystalline grains (devices with complete functions). With the advantage that all the package processes have no special requirement on the structure of packaged chips, therefore the package method has universality, and besides, the device obtained by using the package method is very thin, thus being beneficial to improving the heat dissipation efficiency of chips.

The invention provides a quad flat no-lead (QFN) package which comprises an exposed bonding pad, electrode contacts and reinforcement connection bonding pads. The exposed bonding pad is located in the center of the bottom of the QFN package. The electrode contacts are arranged around the periphery of the QFN package. The four corners of the QFN package are provided with the reinforcement connection bonding pads respectively. According to the QFN package, the reinforcement connection bonding pads are additionally arranged on the four corners of the QFN package, no reinforcement connection bonding pad is arranged on a QFN package in the prior art, the QFN package is connected with a PCB when being used, and the electrode contacts in the QFN package are damaged easily by stress if no reinforcement connection bonding pad is arranged; the reinforcement connection bonding pads are additionally arranged, when the QFN package bears the mechanical stress, the reinforcement connection bonding pads on the four corners and welding spots of the PCB bear the stress firstly, and thus damage to connection between the electrode contacts which are located on the inner side and electrically connected and the PCB can be avoided; the mechanical stress born by the electrode contacts which is located on the inner side due to thermal shock and long-term operation can be lowered, and reliable connection between the electrode contacts on the inner side and the PCB can be kept.