224 results about "Pin array" patented technology

A non-linear fin heat sink is provided for dissipating/removing heat uniformly from a device, where the heat generation is non-uniform over that device, while also providing a small and relatively lightweight heat sink. The heat sink has extended surface protrusions that are optimally shaped in recognition of convective heat transfer, conductive heat transfer, and flow resistance allowing the heat sink to offset the temperature rise of a coolant media and provide enhanced cooling for the coolant temperature, deliver optimized cooling efficiency per the local physical properties of the coolant media, be used with a fluid for effectuating heat transfer; either liquid coolant, gas coolant or a combination thereof. Furthermore the heat sink features turbulence enhancement of the coolant stream by a pin array through which coolant stream passes, such fin array featuring a non-linear shape, spacing, and height pattern to provide optimal cooling while simultaneously reducing volume and flow resistance.

A reinforced solder bump connector structure is formed between a contact pad arranged on a semiconductor chip and a ball pad arranged on a mounting substrate. The semiconductor chip includes at least one reinforcing protrusion extending upwardly from a surface of an intermediate layer. The mounting substrate includes at least one reinforcing protrusion extending upwardly from a ball pad, the protrusions from both the chip and the substrate being embedded within the solder bump connector. In some configurations, the reinforcing protrusion from the contact pad and the ball pad are sized and arranged to have overlapping under portions. These overlapping portions may assume a wide variety of configurations that allow the protrusions to overlap without contacting each other including pin arrays and combinations of surrounding and surrounded elements. In each configuration, the reinforcing protrusions will tend to suppress crack formation and/or crack propagation thereby improving reliability.

A probe card of a wafer test system includes one or more programmable ICs, such as FPGAs, to provide routing from individual test signal channels to one of multiple probes. The programmable ICs can be placed on a base PCB of the probe card, or on a daughtercard attached to the probe card. With programmability, the PCB can be used to switch limited test system channels away from unused probes. Programmability further enables a single probe card to more effectively test devices having the same pad array, but having different pin-outs for different device options. Reprogrammability also allows test engineers to re-program as they are debugging a test program. Because the programmable IC typically includes buffers that introduce an unknown delay, in one embodiment measurement of the delay is accomplished by first programming the programmable IC to provide a loop back path to the test system so that buffer delay can be measured, and then reprogramming the programmable IC now with a known delay to connect to a device being tested.

A semiconductor device and method of fabricating the same. The semiconductor device includes at least one first contact pin on a first substrate and at least one second contact pin on a second substrate. The at least one first and second contact pins may be included in first and second contact pin arrays. The first and second contact pins of the first and second contact pin arrays may be aligned.

A circuit board plug-in subassembly with an LED indicator light of the invention comprises circuit board equipment (9) and an interface device (8) which is arranged at the left side of the circuit board equipment (9). The LED indicator light (10) is arranged at the top of the circuit board equipment (9), and the interface device (8) comprises a shell which is composed of an upper outline part (81) and a lower outline part (82). A contact pin array (99) is arranged at the part of the plate of the circuit board equipment (9) adjacent to the inner side of the shell and is used for engaging with a jack array (72) which is inserted into a plug (7) between the upper outline part (81) and the lower outline part (82) of the interface device (8), and the upper outline part (81) and the lower outline part (82) are respectively engaged with idler wheels (80), which are arranged on an upper sliding block subassembly (83) and a lower sliding block subassembly (84).

A surface replicating and contour measuring device substantially comprises a mechanical pin array having calibration pins mounted on a frame, an imaging system for recording contour and a data processor for storing and manipulating the recorded information.

The invention discloses a corona aging acceleration device and a corona aging acceleration method for a polymer insulating material. The device comprises a sealed corona aging experimental case in which a pin array electrode and a metal plate electrode are arranged, wherein the pin array electrode is connected with a high voltage generation device; the metal plate electrode is grounded; a pinpoint array is arranged on the pin array electrode; a test sample is arranged on the metal plate electrode, and is opposite to the pinpoint array; and after voltage is applied, uniform corona discharge is generated between the pin array electrode and the metal plate electrode to perform corona aging on the test sample. The device and the method have the advantages of low requirements on experimental conditions, convenience for operation and quantitative control over aging factors in an experiment, and short experimental period, and are applied to researches on the corona aging resistance of insulating materials in a laboratory.

A refreshable tactile reader apparatus for Braille text and graphics, utilizing a plurality of compressible tactile pins that can absorb strong downward forces. Such strong forces transmitted through tactile pins can damage pin actuation mechanisms. The physical enclosure of the reader provides open channels that allow the apparatus to be more easily cleaned than prior art enablements.

An integrated circuit generally comprising a plurality of input pads, an input circuit, and a core circuit. The input pads may be configured to receive a plurality of first input signals. The input circuit may be configured to generate a plurality of second input signals (i) equal to the first input signals while in an operational mode and (ii) responsive to a plurality of test vectors with timing generation determined by the first signals while in a test mode. The core circuit may be responsive to the second input signals.

The embodiment of the application discloses a chip and a packaging method thereof. In the chip, the respective first bonding pads on a first bonding pad array on a first substrate are attached to respective corresponding second pins in second pin arrays on different bare chips, thereby achieving short-distance high-density interconnection between bare chips. A plastic package body is used for wrapping first pins, the second pins, the first bonding pads and the first substrate, so that a fan-out unit and the first substrate are plastically packaged into a unitary structure. In the unitary structure, the bottoms of the respective first pins of the first pin array on the bare chips to be electrically connected to the peripheries of the chips are not wrapped in the plastic package body, such that the respective first pins can be directly electrically connected to the peripheries of the chips. The overall size of the chip provided by the embodiment of the application is mainly determined bythe size of the plurality of integrated bare chips. Compared with the prior art, the chip provided by the embodiment of the application is small in overall size, and can meet a chip miniaturization requirement.

The invention belongs to a transdermal drug releasing device field. It relates in particular to a preparing method and usage of the minitype solid silicon pin array chip by monocrystalline silicon and Microelectromechanical systems(MEMS) technology. The minitype solid silicon pin array chip is processed by the adoption of photoengraving, wet etching, plasma dry etching, filming and other MEMS technologies. A side groove opens on the side of the mini pins, one or a plurality of drug storage pool being manufactured on the back of the solid mini pins by the combined utilization of double face alignment light photo technology, the drug dosage can be increased by the connection of the drug storage pool and the solid mini pin surface. The present invention has simple process and durable solid mini pins, being suitable for transdermal drug release of bio drug with macromolecules in particular.

The invention provides a circuit board plug assembly dissipating heat by utilizing heat-dissipation fans. The circuit board plug assembly comprises a circuit board device (9) and an interface device (8) arranged at the left side of the circuit board device (9). The interface device (8) comprises a housing formed by an upper contour portion (81) and a lower contour portion (82); the place, adjacent to the inner side of the housing, of a board body of the circuit board device (9) is provided with an insertion pin array (99) for connecting with insertion hole array (72) in a plug (7) plugged between the upper contour portion (81) and the lower contour portion (82) of the interface device (8); and the upper contour portion (81) and the lower contour portion (82) are connected with roller wheels (80) of an upper slide block assembly (83) and a lower slide block assembly (84) respectively.

An airfoil, a method of manufacturing an airfoil, and a system for cooling an airfoil is provided. The cooling system can be used with an airfoil located in the first stages of a combustion turbine within a combined cycle power generation plant and involves flowing closed loop steam through a pin array set within an airfoil. The airfoil can comprise a cavity having a cooling chamber bounded by an interior wall and an exterior wall so that steam can enter the cavity, pass through the pin array, and then return to the cavity to thereby cool the airfoil. The method of manufacturing an airfoil can include a type of lost wax investment casting process in which a pin array is cast into an airfoil to form a cooling chamber.

A multi-protocol serial interface system comprises a multi-protocol port pin array, a transport protocol change FPGA, a pull-up change FPGA and a memory. The multi-protocol port pin array comprises a plurality of port pins which interface with an external system for exchanging data with the external system. The transport protocol change FPGA determines roles of port pins of the multi-protocol port pin array depending on a variably changed protocol by selecting one of the plurality of programmed transport protocol circuits in response to code data. The pull-up change FPGA regulates pull-up load of the port pins corresponding to the roles of the port pins determined in the transport protocol change FPGA. The memory stores data processed in the transport protocol change FPGA unit and exchanged with the external system.

The invention relates to a fiber array coupled with a VSCEL or PIN array and a manufacturing method of the fiber array. The fiber array comprises a cover slip, a carving groove substrate and a fiber micro-strip, the fiber micro-strip comprises an exposed fiber micro-strip portion without a fiber coating, a V-shaped carving groove for holding the exposed fiber micro-strip portion is formed in the carving groove substrate, the cover slip presses the groove of the exposed fiber micro-strip portion, the carving groove substrate, the cover slip and the exposed fiber micro-strip portion are fixedly connected through binding agents, the cover slip is shorter than the V-shaped carving groove, the end face of the exposed fiber micro-strip portion is an optical plane with a 45-degree oblique angle, and the optical plane faces the carving groove substrate. The coupling distance between the 45-degree optical plane of the exposed fiber micro-strip portion and the VSCEL or PIN array is controlled by the aid of the cover slip of the fiber array, the thickness of the cover slip can be customized, and high-efficiency coupling is realized. The method for manufacturing the fiber array is simple, easy to implement and low in cost.

An electrical connector assembly is provided for mating with electrical plugs. The electrical connector assembly includes a housing having a top wall and a bottom wall that is opposite the top wall. The housing includes a mating face having ports that are configured to receive the electrical plugs therein. A jack sub-assembly is held by the housing. The jack sub-assembly includes jacks having electrical contacts held within the ports for engagement with the electrical plugs. The jack sub-assembly includes a signal pin array having signal pins for connection to a host circuit board. The signal pin array includes a front side extending along the bottom wall of the housing. An electrically conductive outer shield covers the top wall of the housing. The outer shield includes a bottom flap covering an end of the bottom wall of the housing. An electrically conductive bottom shield covers the bottom wall of the housing between the bottom flap of the outer shield and the front side of the signal pin array.

An antenna connection function for a noncontact interface is provided by suppressing a modification in a pin arrangement and a pin shape of a memory card that does not correspond to the noncontact interface. Two antenna connecting pins having the memory card are divided into two areas in which a size of one potential supply pin is the largest and used as a split pin arranged at intervals. Because a size of the two antenna connecting pins is at maximum as large as the size of the potential supply pin, the two antenna connecting pins are provided and the memory card that corresponds to the noncontact interface is obtained by devoting a pin area having the size of the one potential supply pin to the memory card that does not correspond to the noncontact interface. Accordingly, the pin area of the memory card that corresponds to the noncontact interface can be formed without departing from the pin area of the memory card that does not correspond to the noncontact interface.

The invention relates to a circuit board plug-in component with a roller groove. The circuit board plug-in component comprises circuit board equipment (9) and an interface device (8) disposed on the left side of the circuit board equipment (9). The interface device (8) comprises a shell formed by an upper contour part (81) and a lower contour part (82). A part, adjacent to the inner side of the shell, of the board of the circuit board equipment (9) is provided with a contact pin array (99) used for being connected with the jack array (72) of a plug (7) inserted between the upper contour part (81) and the lower contour part (82) of the interface device (8). The upper contour part (81) and a lower contour part (82) are respectively connected with rollers (80) on an upper slider component (83) and a lower slider component (84).

The invention provides a multilayer wiring substrate/multi-chip integration-based large port interconnection chip interconnection construction and physical realization method and relates to a multi-chip interconnection structure, a multi-chip interconnection structure construction method, multi-chip layout, substrate pin array partitioning and distribution, distribution of high-speed differential signal pin pairs, effective partition of substrate wiring and a partition method of the substrate wiring as well as a corresponding multi-chip interconnection chip device which are applicable to substrate integration. According to the invention, large-port interconnection chips can be effectively and equivalently realized based on substrate encapsulation size. Compared with a corresponding single-chip integration implementation method, the method of the invention can support multiple kinds of interconnection structures, and is compatible with interconnection sub-chips be of a variety of micro-system structures, can effectively utilize the characteristics of different functional interconnection sub-chips, and has better performance in implementation cost of the chips, scalability, flexibility, compatibility and the like; and at the same time, the method of the invention has lower requirements for manufacturing technology for realizing a required integrated circuit and can provide interconnection chips having different specifications and different number of ports, and can more flexibly adapt to market demands.

The invention discloses a QFN (quad flat non-lead) package with multiple circles of pins and a manufacturing method thereof. The package comprises a lead frame, metal material layers, an IC (integrated circuit) chip, an insulated filling material, an adhesive material, metal conductors and a plastic package material, wherein the lead frame comprises a chip carrier and multiple pins which are arranged around the chip carrier for multiple circles; the metal material layers are arranged on the upper surface and lower surface of the lead frame; the IC chip is arranged on the metal material layer on the upper surface of the lead frame; the insulated filling material is arranged below a stepped structure of the lead frame; the adhesive material is arranged between the IC chip and the metal material layer on the upper surface of the lead frame; the IC chip is respectively connected with inner pins of the multiple circles of pins and the upper surface of the chip carrier by the metal conductors; and the plastic package material coats and seals the IC chip, the adhesive material, the metal conductors, parts of regions of the lead frame and parts of metal material layer. According to the invention, the bottleneck of the low I/O (input/output) quantity can be broken through, and the sealing reliability is improved.

The invention relates to a low-dimensional nanophase material high-flexibility assembling chip and an application method, which belong to the micro-fluidic field and the nano structure material assembly field. The method realizes the electric field distributing control in a micro-fluidic body (4) according to the following two aspects to further generate micro force used for realizing assembly control: one the one hand, the on-off control of pumping signal of each pin in a pin array (11) is controlled to realize that only some microelectrode arrays (13) have electric potential so as to further change the area size of the effective bounding region of the electric field at the top of the chip; and on the other hand, a virtual aurora pattern array is projected on a photoconductive layer (32) by a micro light pattern generator (5) to further limit the electric field boundary at the bottom of the micro-fluidic body (4) in the chip.