Chip and packaging method thereof

Abstract

The embodiment of the application discloses a chip and a packaging method thereof. In the chip, the respective first bonding pads on a first bonding pad array on a first substrate are attached to respective corresponding second pins in second pin arrays on different bare chips, thereby achieving short-distance high-density interconnection between bare chips. A plastic package body is used for wrapping first pins, the second pins, the first bonding pads and the first substrate, so that a fan-out unit and the first substrate are plastically packaged into a unitary structure. In the unitary structure, the bottoms of the respective first pins of the first pin array on the bare chips to be electrically connected to the peripheries of the chips are not wrapped in the plastic package body, such that the respective first pins can be directly electrically connected to the peripheries of the chips. The overall size of the chip provided by the embodiment of the application is mainly determined bythe size of the plurality of integrated bare chips. Compared with the prior art, the chip provided by the embodiment of the application is small in overall size, and can meet a chip miniaturization requirement.

Description

technical field [0001] This field relates to the technical field of semiconductor packaging, in particular to a chip and a packaging method. Background technique [0002] With the continuous development of integrated electronic technology, the requirements for chip performance are also increasing, such as function enhancement, size reduction, energy consumption and cost reduction, etc., thus giving birth to 3DIC (Three Dimensional Integrated Circuit, three-dimensional integrated circuit) technology. Silicon Interposer (Silicon Interposer) technology is a technical solution to realize the interconnection of stacked chips in three-dimensional integrated circuits. This technical solution uses semiconductor technology to manufacture interconnection lines on silicon wafers with much smaller line width and node spacing than resin substrates. In this way, chips with different functions such as CPU and DRAM can be connected to the same silicon interposer, and a large number of calc...

AI Technical Summary

Problems solved by technology

[0005] However, in the existing fan-out wafer-level packaging structure, the pins on the bare chip that are used to electrically connect to the periphery of the packaging structure need to pass through the substrate to realize the electrical connection with the periphery of the packaging structure. In this way, the overall size of the packaging structure Larger, cannot meet the needs of chip miniaturization

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