35 results about "Array Feature" patented technology

This disclosure relates to CryoArrays, which permit the analysis of samples (such as protein, nucleic acid, virus, or cell samples) in arrays that are prepared at low temperatures. Because CryoArrays are constructed as a block of substantially columnar samples, the block can be sliced to provide a plurality of identical or substantially identical individual arrays. The individual arrays can be used for parallel analysis of the same array feature set, for instance with different probes or under different conditions. Also provided are methods of making CryoArrays, devices for making CryoArrays, and kits.

A method, apparatus for executing the method, and computer program products for use in such an apparatus. The method includes scanning an interrogating light across multiple sites on an array package including an addressable array of multiple features of different moieties, which scanned sites include multiple array features. Signals from respective scanned sites emitted in response to the interrogating light are detected. The interrogating light power is altered for a first site on the array package during the array scan, based on location of the first site or on a determination that the emitted signal from the first site will be outside a predetermined value absent the altering (which allows for protecting a detector against expected overly bright sites), or is altered during the array scan based on the detected interrogating light power (which allows for compensating for light source drift during an array scan).

The invention discloses an optimization method of a sparse circular antenna array. The optimization method of the sparse circular antenna array comprises the following steps: (1) producing individuals by adopting an indirect method to establish an initial population; (2) performing genetic pretreatment to the population; (3) performing generalized crossing and generalized variation to the population; (4) performing genetic post-treatment to the population and selecting superior individuals according to fitness; (5) performing iterative optimization to obtain optimum individuals and maximum peak side lobe level. The circular array optimized by adopting the method is characterized in that array elements are non-uniformly distributed on the diameter of a circular hole and are not limited to an auxiliary circular ring. The method can utilize the degree of freedom of the array elements to a larger extent, is higher in efficiency than the traditional genetic algorithm and can enable the antenna array to obtain lower side lobe level.

Methods for correcting systematic errors in the measured position of deposited features of a nucleic acid array on a substrate. Systematic errors are modeled by an algorithmic model based on measuring the positions (and possibly other properties) of a subset of the features, and a model is constructed for predicting deviations in feature position from an ideal grid. Deviations arising in the deposition process, the scanning process, or both may be corrected.

Indexable optical fiber connectors, optical connector arrays, and optical connector systems are disclosed. According to one embodiment, an optical fiber connector includes a connector body comprising an optical coupling face and a connector housing that surrounds the connector body. The connector housing includes a first interconnecting surface having an indentation arraying feature, and a second interconnecting surface having a protrusion arraying feature. The first interconnecting surface and the second interconnecting surface are orthogonal to the optical coupling face. The indentation arraying feature is configured to mate with a corresponding protrusion arraying feature of a first adjacent interconnecting optical fiber connector by a non-locking engagement relationship. Similarly, the protrusion arraying feature is configured to mate with a corresponding indentation arraying feature of a second adjacent optical fiber connector by a non-locking engagement relationship.

Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and / or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

Methods for correcting systematic errors in the measured position of deposited features of a nucleic acid array on a substrate. Systematic errors are modeled by an algorithmic model based on measuring the positions (and possibly other properties) of a subset of the features, and a model is constructed for predicting deviations in feature position from an ideal grid. Deviations arising in the deposition process, the scanning process, or both may be corrected.

An antenna array formed of individual electrically connected pluralities of wideband antenna elements. The array features a centrally located rectangular ground plane having a top surface defined by four edges. Each of said pluralities of elements is engaged to a separate substrate which is engaged along one of the four edges. The substrates may be angled to adjust the footprint of the antenna.

Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and / or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

The invention provides an MBD model array feature quick annotation method for digital detection and relates to the field of digital detection technology. According to the method, first, uniform sampling is performed on a group of array features on an MBD model, and sampling point clouds are obtained; second, a PCA algorithm and an improved ICP algorithm are adopted to perform rough registration and precise registration among the sampling point clouds, and a matching relation among the sampling point clouds is determined; and last, complementing of annotation information missed by the array features is completed according to the corresponding relation among the sampling point clouds. Through the MBD model array feature quick annotation method for digital detection, on the basis of not intervening an annotation habit of a designer on the array features of the MBD model, complementing of the missing information is automatically completed, the efficiency and accuracy of array feature sizeannotation are improved, array feature objects annotated through the quick annotation method meet the requirement of measurability, and one-to-one correspondence between to-be-checked objects and detection requirements is realized.

A method for forming patterns of a semiconductor device includes preparing an etch target layer defined with a first region and a second region; forming a regular first feature which is positioned over the etch target layer in the first region and a random feature which is positioned over the etch target layer in the second region; forming a regular second feature over the regular first feature; forming first and second cutting barriers which expose a portion of the random feature, over the random feature; cutting the regular first feature using the regular second feature, to form a regular array feature; cutting the random feature using the first cutting barrier and the second cutting barrier, to form a random array feature; and etching the etch target layer by using the regular array feature and the random array feature, to form a regular array pattern and a random array pattern.

The development of a flat panel display (FPD) process technology, especially the popularization of an In Cell touch screen design process puts forward a severe challenge for a full-panel design tool. With the increment of a resolution and a panel size, direct application of a high-precision numerical analysis-based capacitance extraction method to capacitance calculation of a full-panel layout is very time-consuming, and the speed cannot meet the design requirement. The invention provides an array-based full-panel layout capacitance quick extraction method. By utilizing an array feature of the layout, the capacitance extraction of the full-panel layout is accelerated through a method for division of an array region and a non array region, division and extraction of the non array region, extraction of an array unit of the array region and final capacitance combination calculation, so that the problem of excessively time-consuming and even unfeasible full-panel layout capacitance extraction caused by a complex graph and excessive scale is solved.

The invention provides a digital detection-oriented MBD model array feature rapid labeling method, which relates to the technical field of digital detection. This method first uniformly samples a group of array features on the MBD model to obtain the sampling point cloud; then uses the PCA algorithm and the improved ICP algorithm to perform coarse registration and precise registration between the sampling point clouds, and establishes the relationship between the sampling point clouds. Matching relationship; finally, according to the corresponding relationship between the sampled point clouds, complete the missing labeling information of the array features. The digital detection-oriented MBD model array feature rapid labeling method provided by the present invention automatically completes the missing information on the basis of not interfering with the designer's habit of marking the MBD model's array feature, and improves the efficiency of array feature dimension labeling and accuracy, so that the array feature objects marked by the rapid labeling method meet the requirements of measurability, and realize the one-to-one correspondence between the objects to be inspected and the inspection requirements.

The invention discloses a signal processing two-dimensional data array feature enhancing and data compressing method which comprises a step of parameter calculation, a step of small array calculation, a step of feature point calculation and the like. Via the signal processing two-dimensional data array feature enhancing and data compressing method, two-dimensional data array feature points can be enhanced and a total quantity of data can be compressed; the method is characterized by concise procedures, high speed, high execution efficiency, and synchronous completion of feature enhancing operation and data compressing operation.

The invention discloses a TiO2 nuclear shell structure nano rod array coated with carbon bed, the core of the nano rod is TiO2 nano rod, the diameter thereof is 20-100nm, the shell thereof is the carbon bed, the thickness thereof is 2-10nm. The preparation method has the following steps: a) under the condition of solvent heat condition, interface reaction of non-polar solvent / hydrophilic matrix is employed to prepare the TiO2 nano rod with surface modified by oleic acid; b) with the protection of inert gas, warming calcination is carried out to obtain the TiO2 nuclear shell structure nano rodcoated with carbon bed. The invention has the following beneficial effects: under the condition of solvent heat condition, interface reaction of non-polar solvent / hydrophilic matrix is employed to prepare the TiO2 nano rod with surface modified by oleic acid, then warming calcination is carried out to carbonize oleic acid on the surface to prepare the TiO2 nuclear shell structure nano rod array coated with carbon bed, with such steps, the invention features simple process and low cost, can prepare a large area of TiO2 nano rod array; in addition, the nano rod array features good crystallization performance, large specific surface area, is beneficial to improving charge capacity of the dye, adsorption to pollutants, charge separation of a photoproduction current carrier and increasing quantum yield, thus being capable of being widely applied to fields such as photocatalysis and O / E conversion.

The invention relates to a four-camera plane array feature point matching method and a measurement method based on the four-camera plane array feature point matching method, belonging to the field of optical and electronic measurement. The matching method includes taking one of the four image planes as the base image plane, and finding a feature point that matches the feature point on an image plane adjacent to the base image plane in the lateral direction for a feature point on the base image plane. All matching points; for the feature points on the base image plane, find out all the matching points that match the feature points on the image plane adjacent to the base image plane in the longitudinal direction; all the found horizontal and vertical directions The matching points are re-matched to find out all sub-matching point groups; find out the matching points corresponding to the feature points on the diagonal position image plane and the base image plane and all found sub-matching point groups; determine the matching points in the four image planes A unique matching point group corresponding to the same viewpoint. For each unique matching point group, the three-dimensional space coordinates of the viewpoint can be calculated according to the image coordinates of the matching point group and the parameters of the camera system itself. Under any lighting conditions, as long as the collected images are clear enough, for any object that is imaged on the image of the four-camera planar array and has certain image characteristics, the exact same matching method and measurement method can be used to achieve the object’s detection. 3D measurement.

Due to the development of touch screen and pixel design technologies, the resolution is increasingly high, the size is increasingly large, and a more severe challenge is provided to the rate of extraction of the resistance capacitance from the full-panel layout. The extraction of the resistance capacitance from the full-panel layout by directly using the traditional numerical analysis method is too time-consuming. The extractive process can be accelerated by using a simple-structure multiplexing-array layout. However, difficulty is brought for array-based extraction methods due to unremarkable array features of an original layout. The invention provides a multiplexing-array layout generation method, and the original layout is decomposed into multiplexing-array-containing new layouts through multiplexing pattern element size selection, layout cutting, area grouping and new layout generation technologies by using repeated pattern features. Thus, an array structure of the full-panel layout is reconstructed, and the method is used for accelerating the extraction of the resistance capacitance from the full-panel layout.