Memory cell with polysilicon local interconnects

Abstract

Methods and apparatus are described to facilitate forming memory devices with low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source regions of array transistors. By providing for a local interconnect of polysilicon, a smaller source region and / or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

Description

RELATED APPLICATION [0001] This Application is a Divisional of U.S. application Ser. No. 10 / 714,752, titled “METHOD FOR FORMING POLYSILICON LOCAL INTERCONNECTS,” filed Nov. 17, 2003, (pending) which is commonly assigned and incorporated herein by reference.TECHNICAL FIELD OF THE INVENTION [0002] The present invention relates generally to integrated circuit devices and, in particular, to the formation of local polysilicon interconnects for a semiconductor memory device. BACKGROUND OF THE INVENTION [0003] Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address. [0004] There are several different types of memory used in modem electronics, one common...

AI Technical Summary

Benefits of technology

[0011] Various embodiments of the invention facilitate forming of low resistance polysilicon local interconnects that allow a smaller array feature size and therefore facilitate forming arrays of a denser array format. Embodiments of the present invention are formed utilizing a wet etch process that has a high selectivity, allowing the deposition and etching of polysilicon local interconnects to source and drain regions of array transistors. In addition, by forming local interconnects and contacts to the source regions of array elements with a high selectivity etch the size of the area dedicated to each interconnect line is reduced, thus allowing the use of a smaller pitch, i.e., a smaller spacing between adjacent word lines. By providing for a local interconnect of polysilicon, a smaller source region and / or drain region can also be utilized, further decreasing the required word line spacing. Low resistance polysilicon local source interconnects can also couple to an increased number of memory cells, thereby reducing the number of contacts made to an array ground.

Problems solved by technology

Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents.

As soon as the power is turned off, whatever data was in RAM is lost.

However, both of these approaches have exhibited issues that make them problematic in their reducing feature size; local interconnect lines formed of polysilicon or metal are often difficult and expensive to process in increasingly narrow trench areas and diffusing enough dopant to form a conduction line of a sufficiently low resistance can form deep and broad region junction areas that make it difficult to shrink the cell gate area.

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