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Array-based full-panel layout capacitance quick extraction method

An extraction method and capacitor technology, which can be used in electrical digital data processing, special data processing applications, instruments, etc., and can solve problems such as losing array rules.

Inactive Publication Date: 2017-06-13
北京华大九天科技股份有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The layout will be formed by superimposing multiple array instances. Although each array instance is an array structure, the superposition of all arrays will lead to loss of array regularity

Method used

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  • Array-based full-panel layout capacitance quick extraction method
  • Array-based full-panel layout capacitance quick extraction method
  • Array-based full-panel layout capacitance quick extraction method

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example

[0016] Combined with a specific instance method, the operation process steps are as follows:

[0017] 1) Open a hierarchical layout with a simple structure;

[0018] 2) Select the wire mesh to be extracted;

[0019] 3) For the proposed wire net, find the non-array area and the array area that have passed through, and record the index in the array;

[0020] 4) For the non-array area, divide and extract the capacitance of the effective area, and record the intermediate results;

[0021] 5) For the array area, perform capacitance extraction for each valid array unit, and record the intermediate results;

[0022] 6) Combine the final result, that is, combine the capacitance value of the array area and the capacitance value converted from the internal capacitance value of the array unit to the corresponding external wire net.

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Abstract

The development of a flat panel display (FPD) process technology, especially the popularization of an In Cell touch screen design process puts forward a severe challenge for a full-panel design tool. With the increment of a resolution and a panel size, direct application of a high-precision numerical analysis-based capacitance extraction method to capacitance calculation of a full-panel layout is very time-consuming, and the speed cannot meet the design requirement. The invention provides an array-based full-panel layout capacitance quick extraction method. By utilizing an array feature of the layout, the capacitance extraction of the full-panel layout is accelerated through a method for division of an array region and a non array region, division and extraction of the non array region, extraction of an array unit of the array region and final capacitance combination calculation, so that the problem of excessively time-consuming and even unfeasible full-panel layout capacitance extraction caused by a complex graph and excessive scale is solved.

Description

technical field [0001] Array-based rapid extraction of full-board layout capacitance is a method for full-board capacitance extraction, and the invention belongs to the field of EDA design. Background technique [0002] With the rapid development of flat panel display (FPD) process technology, especially the popularity of the In Cell touch screen design process, the capacitance extraction for the full board layout poses a great challenge to FPD design tools. In order to improve the calculation accuracy, the capacitance extraction tool usually adopts the numerical analysis method based on the field solution, which is relatively slow. With the increase of the resolution and the increase of the design size, the scale of the overall board layout is getting larger and larger, and the complexity of the graphics is also getting higher and higher. In this way, for the capacitance extraction of the full board layout, the conventional method is very time-consuming, and the speed cann...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
CPCG06F30/392
Inventor 贾艳明赵威陆涛涛
Owner 北京华大九天科技股份有限公司
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