Area array quad flat no lead package (AAQFN) package body package in package (PiP) piece with solder balls and production method

A technology of leadless packaging and spherical arrays, which is applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve problems such as unsatisfactory short-term requirements, difficult frame manufacturing process, and long R&D cycle to reduce production The effect of reducing costs and shortening the R&D cycle

Active Publication Date: 2014-04-16
TIANSHUI HUATIAN TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] Although China has begun to develop multi-turn QFN in the past two years, due to the difficulty of frame manufacturing process, only a few foreign suppliers can design and produce it, but it is still limited by the patents of rel...

Method used

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  • Area array quad flat no lead package (AAQFN) package body package in package (PiP) piece with solder balls and production method
  • Area array quad flat no lead package (AAQFN) package body package in package (PiP) piece with solder balls and production method
  • Area array quad flat no lead package (AAQFN) package body package in package (PiP) piece with solder balls and production method

Examples

Experimental program
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Effect test

preparation example Construction

[0046] The preparation method of a kind of above-mentioned package that the present invention provides, specifically carries out according to the following steps:

[0047] Step 1: Thinning Scribing:

[0048] Using 8-inch to 12-inch thinning machine, using rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 180μm-200μm; the rough grinding speed is 6μm / s, and the fine grinding speed is 1.0μm / s; using rough grinding, fine grinding and polishing anti-warping process, the wafer without bumps is thinned to 50 μm ~ 75 μm, the rough grinding speed is 3 μm / s, and the fine grinding speed is 6.0 μm / min; the chip is prevented from warping Qu craft;

[0049] Use the A-WD-300TXB dicing machine to dicing the thinned 8-inch to 12-inch wafers, and the dicing feed speed is ≤10mm / s;

[0050] Step 2: On the dry film placement machine, paste the dry film film 26 on the front of the bare copper frame 1, and bake it at a temperature of 35°C to ...

Embodiment 1

[0067] Using 8-inch to 12-inch thinning machine, adopts rough grinding, fine grinding and polishing anti-warping process, the wafer with bump chip is thinned to 200 μm, the rough grinding speed is 6 μm / s, and the fine grinding speed is 1.0 μm / s ;Using rough grinding, fine grinding and polishing anti-warping process, the wafer without bump chip is thinned to 75 μm, the rough grinding speed is 3 μm / s, and the fine grinding speed is 6.0 μm / min; the chip warping prevention process is adopted; A-WD-300TXB dicing machine is used for scribing, and the scribing speed is ≤10mm / s. Use a dry film sticking machine to stick the dry film on the front of the bare copper frame and bake it at 35°C for 20 minutes. Then, align, expose, develop, and fix the bare copper frame with the dry film on the exposure machine, display the pattern on the bare copper frame, and then harden the film at a temperature of 85°C for 30 minutes; then etch and clean On the machine, by spraying acidic etching soluti...

Embodiment 2

[0069] In the process of wafer thinning and dicing, the final thinning thickness of the wafer with bumps is 180 μm; the final thinning thickness of the wafer without bumps is 50 μm, and the rest are the same as in Example 1; Paste the dry film 26 on the front of the bare copper frame 1, and bake at a temperature of 60°C for 10 minutes; The second groove 27 and the third groove 28 with a pattern are shown on the copper frame 1, and the film is hardened for 35 minutes at a temperature of 80° C.; then a UBM composed of three metal layers is prepared according to the method of Example 1 1 Layer 33 and lead frame pad 10, the three-layer metal layer is the first metal layer, the second metal layer and the third metal layer arranged in sequence, the first metal layer is Ni layer, the second metal layer Cr layer, the third metal layer The metal layer is an Au layer, and the first metal layer is in contact with the bare copper frame 1; then the stacked package with a soldered ball arra...

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Abstract

Provided are an area array quad flat no lead package (AAQFN) package body package in package (PiP) piece with solder balls and a production method. The AAQFN package body PiP piece with the solder balls comprises a bare copper frame with multiple pits, an IC chip with salient points is mounted on the front face of the bare copper frame inversely, lower packing is filled between the salient points of the chip and the pits, a first groove is formed in the bare copper frame, two leads which are not connected with each other are formed on the two sides of the first groove, plastic package is carried out on the IC chips with salient points, connecting layers connected with the corresponding leads are arranged on the lower faces of the leads, the solder balls are arranged on the surfaces of all the connecting layers, two layers of IC chips are attached to a first plastic package body, the two layers of IC chips are connected through bonding wires and are connected with the leads through bonding wires respectively, and secondary plastic package is carried out. Through the working procedures of wafer thinning and dicing, bare copper frame processing, upper chip inverse mounting, passivation layer coating and etching, chemical sedimentation and the like, the AAQFN package body PiP piece with the solder balls is prepared. The PiP piece product is smaller in size, higher in packaging density, more in function and capable of replacing parts of BGA PiP and CSP PiP.

Description

technical field [0001] The invention belongs to the technical field of electronic information automation components, and in particular relates to an Area Array Quad Flat No Lead Package (AAQFN for short) package stacked package (Package on Package, PoP for short); The invention also relates to a method for preparing the package. Background technique [0002] Although China has begun to develop multi-turn QFN in the past two years, due to the difficulty of frame manufacturing process, only a few foreign suppliers can design and produce it, but it is still limited by the patents of related companies, relatively few pins, and long development cycle. And packaging multi-turn QFN is limited to lead frame manufacturers, which cannot meet the requirements of short, flat, fast, and flexible application of different chips. In order to eliminate the pin limitation of the peripheral lead structure in the past, it meets the needs of high-density, multi-I / O packaging. Develop an Area A...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L21/60H01L25/16
CPCH01L2224/73253H01L2224/48145H01L2224/48091H01L2224/73265H01L2924/00014H01L2924/00012
Inventor 慕蔚李习周邵荣昌张进兵
Owner TIANSHUI HUATIAN TECH
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