363results about How to "Guaranteed ease of operation" patented technology

A safety sensing system for a compartment of a vehicle is operable to detect an occupant within the vehicle compartment. The system may be operable to sense ambient conditions in the vehicle compartment, and may generate a control signal in response to the sensed conditions. The system may actuate indicators to notify operators of the vehicle that there is a person or animal detected in the compartment. Optionally the system may open the vehicle compartment in response to a detection of an occupant and the sensed conditions. The safety system includes a false trigger protection means that limits or reduces false detections of a person or animal within the compartment.

A system and method classifies packets with a programmably fixed network processor program and dynamically updated data structures. The network processor program selects predetermined packet field values of the packets transmitted across the network and classifies the packets by matching one or more packet field values with a data structure. New packet classifications are dynamically created by updating the data structure to associate one or more predetermined packet field values with the new packet classification. For instance, a parse tree program extracts packet header information and matches the packet header information to the data structure. A pattern tree data structure provides longest prefix matches and an ordered tree data structure provides combination matches so that classification of arbitrary Boolean combinations of extracted header fields can be formed.

The invention relates to an orthopedic compression screw, in particular a compression screw for osteosynthesis and/or fixation of bone segments (12, 14), with a threaded portion (20) and a screw head (18), the screw head (18) widening conically toward its distal end and the screw being provided along its longitudinal axis (A) with a bore (26) for interaction with an orthopedic guide element, in particular a guide wire, and the periphery of the screw head (18) having at least one flat that forms a plane outer surface (30) preferably extending parallel to the longitudinal axis.

Methods and systems are provided for controlling the automatic shutdown of an idling vehicle engine. When the vehicle is parked in an enclosed space, the idling engine may be automatically shutdown, while when the vehicle is parked in an open space, the automatic shutdown may be delayed based on an ambient temperature. In this way, the vehicle cabin may be maintained at a temperature that provides enhanced driver comfort while allowing wasteful engine idling to be reduced.

In a coating unit, a piezovalve driven by piezoelectric elements is used as an opening and closing valve 79. The use of the piezovalve which can nearly disregard delay time makes it possible to accurately control the time of working the opening and closing valve 79 and to finely control working speed thereof at the time of opening and closing the valve. Therefore, operation necessary for closing the valve can be slowly performed, thus appropriately preventing dripping of a resist solution and occurrence of bubbles in a resist solution by air which enters from a forward end of a resist nozzle 60.

Embodiments of the invention provide techniques for managing cache metadata providing a mapping between addresses on a storage medium (e.g., disk storage) and corresponding addresses on a cache device at data items are stored. In some embodiments, cache metadata may be stored in a hierarchical data structure comprising a plurality of hierarchy levels. Only a subset of the plurality of hierarchy levels may be loaded to memory, thereby reducing the memory “footprint” of cache metadata and expediting the process of restoring the cache metadata during startup operations. Startup may be further expedited by using cache metadata to perform operations associated with reboot. Thereafter, as requests to read data items on the storage medium are processed using cache metadata to identify addresses at which the data items are stored in cache, the identified addresses may be stored in memory. When the computer is later shut down, instead of having to transfer the entirety of the cache metadata from memory to storage, only the subset of the plurality of hierarchy levels and/or the identified addresses previously loaded to memory may be transferred (e.g., to the cache device), thereby expediting the shutdown of the computer.

A digital circuit which can operate normally regardless of binary potentials of an input signal is provided. A semiconductor device comprising a correcting unit and one or a plurality of circuit elements, the correcting unit including a first capacitor, a second capacitor, a first switch, and a second switch, wherein the first electrode of the first capacitor is connected to an input terminal, the supply of a first potential to the second electrode of the first capacitor is controlled by the first switch, the supply of a second potential to the second electrode of the second capacitor is controlled by the second switch, and a potential of the second electrode of the first capacitor or a potential of the second electrode of the second capacitor is supplied to the one or the plurality of circuit elements.

A base address sorting device in a serial switch is disclosed which includes an array of shadow registers, each shadow register in the array being electrically coupled to a base address register, in an array of base address registers, each of the base address registers having a base address, and control logic circuitry electrically coupled to the array of shadow registers and to the array of base address registers with the control logic circuitry being operable, when it receives a configuration command, to implement a method, for reconfiguring the contents of the array of base address registers, including: inserting a new base address from the configuration command into a shadow register in the array of shadow registers, sorting the array of shadow registers into a predetermined order, and then copying the contents of the array of shadow registers into the array of base address registers.

A two-port SRAM memory cell includes a pair of cross-coupled inverters coupled to storage nodes. An access transistor is coupled between each storage node and a write bit line and controlled by a write word line. The write word line is also coupled to a power supply terminal of the pair of cross-coupled inverters. During a write operation, the write word line is asserted. A voltage at the power supply terminal of the cross-coupled inverters follows the write word line voltage, thus making it easier for the stored logic state at the storage nodes to change, if necessary. At the end of the write operation, the write word line is de-asserted, allowing the cross-coupled inverters to function normally and hold the logic state of the storage node. Coupling the power supply node of the cross-coupled inverters allows faster write operations without harming cell stability.

A method of manufacturing a flash memory is provided. First, a substrate with a first gate structure and a second gate structure thereon is provided. The first gate structure and the second gate structure each comprises of a dielectric layer, a first conductive layer and a cap layer. A tunneling oxide layer is formed over the substrate and then a first spacer is formed on the sidewall of the first conductive layer. Thereafter, a second conductive layer is formed on one side designated for forming a source region of the sidewalls of the first gate structure and the second gate structure. Then, the source region is formed in the substrate in the designated area. Next, an inter-gate dielectric layer is formed over the second conductive layer and then an insulating layer is formed over the source region. After forming a third conductive layer over the area between the first gate structure and the second gate structure, a drain region is formed in the substrate.

The invention provides a method for managing the data in the removable storage device. The method includes: applying or organizing or establishing or re-building the file managing system of the storage medium of said removable storage device according to the uses of said memory chips; and utilizing said file managing system to perform the corresponding processing in said memory chips according to the operation instructions of the host system, which is connected with said file managing system. By applying the method for managing the data in the removable storage device, which the invention provides, the capacity of the removable storage device can be extended, and the storage medium can be updated, thus the data security, the functions and the convenience of the system are increased.

The invention discloses a forest fire early warning method and system based on a fuzzy Bayesian network and belongs to the fire-fighting safety field. The method comprises the following steps that anunmanned aerial vehicle is equipped with a plurality of sensors to inspect a forest along a set route, senses data of a driving area in real time and sends the data to a ground station; the ground station combines the number of local sunny days and the number of flammable plants to carry out stage treatment on flammable grades, and carries out early judgment of fire warning according to temperature, humidity, smoke and gas information; the ground station receives the data of each sensor, then uses a fuzzy Bayesian network to process the sensor data, and calculates and acquires a fire occurrence probability; when the probability of the fire is high, the ground station sends a fire warning signal, whether there is the fire, a real-time situation of the fire and location information to a forest management center; and when the probability of the fire is low, the unmanned aerial vehicle flies at the same height along the set route. In the invention, a fuzzy Bayesian network algorithm is used to process the sensor data, the fire probability can be accurately calculated so that correlation personnel can accurately acquire a fire condition at first time.

A path configuration for a power switch and driver can introduce independent parasitic inductance coupled to the power switch to slow a switching speed of the switch and reduce voltage spikes on the switch during switching events. The path for low side supply of the drive to the negative DC voltage reference is separate from the path of the power switch to the reference. The resulting reduction in voltage spikes due to the slowed switching time maintains performance in an audio amplifier without modifying a switch command signal to compensate for voltage spikes. The path configuration avoids reliance on specifying higher rated components that increase application costs.

An input device includes an operation unit, a sending unit, and a power control unit. The operation unit is configured to be held by a user and to be operated in a three-dimensional free space so as to remotely operate an information processing apparatus. The sending unit is configured to send a command that disables display of a graphical user interface of the information processing apparatus when the operation unit is placed, and to send a command that enables display of the graphical user interface of the information processing apparatus when a button of the operation unit is operated. The power control unit is configured to cause the input device to enter a low power consumption state when the operation unit is placed.

A tape measure is disclosed which has a spooled measuring blade mounted via a rotatable connection within a casing. The blade is extended from the case via an opening for use. The blade can be braked with respect to the opening by operation of braking means. The braking means are operable via a switch which has a length greater than the radius of the fully spooled blade. The switch is located and sized so that the brake can be engaged or disengaged by a user's hand without changing grip. The brake is a cam brake rotatably connected to the switch via a push-pull member.

It is an object of the invention to provide a digital circuit which can operate normally regardless of binary potentials of an input signal. A semiconductor device having a correcting unit and a logic unit wherein the correcting unit includes a capacitor, first and second switches, wherein the first electrode of the capacitor is connected to the input terminal and the second electrode of the capacitor is connected to the gate of the transistor in the logic circuit, wherein the first switch controls the connection between a gate and drain of the transistor and the second switch controls the potential to be supplied to the drain of the transistor is provided.