Methods of forming semiconductor constructions and integrated circuits

Abstract

The invention includes a TFT-based logic circuit construction. Such construction includes a pair of first transistor devices, and a pair of second transistor devices over the first transistor devices. The first transistor devices have first active regions extending into a first semiconductive material, and the second transistor devices have second active regions extending into a second semiconductive material. At least one of the first and second semiconductive materials can comprise crystalline Si / Ge. The logic construction can comprise NOR circuitry and / or NAND circuitry, as well as higher level logic cells, such as latches. Further, the logic circuit construction can be associated with a semiconductor-on-insulator structure, and on versatile substrates. The invention includes three-dimensional logic cell layout configurations for enhanced wireability and logic cell density, which can lead to enhanced performance.

Description

RELATED PATENT DATA [0001] This patent resulted from a continuation application of U.S. patent application Ser. No. 11 / 130,742, which was filed May 17, 2005, and which is hereby incorporated by reference; which resulted from a continuation application of U.S. patent application Ser. No. 10 / 387,090, which was filed Mar. 11, 2003, issued as U.S. Pat. No. 6,900,667, and is hereby incorporated by reference.TECHNICAL FIELD [0002] This disclosure relates generally to integrated circuits. In particular aspects, the invention pertains to logic devices. The logic devices can be utilized in electronic systems; and can be incorporated into, for example, processor devices for computer systems. BACKGROUND OF THE INVENTION [0003] SOI technology differs from traditional bulk semiconductor technologies in that the active semiconductor material of SOI technologies is typically much thinner than that utilized in bulk technologies. The active semiconductor material of SOI technologies will typically b...

AI Technical Summary

Problems solved by technology

A problem associated with conventional TFT constructions is that grain boundaries and defects can limit carrier mobilities.

High voltage (and therefore high power consumption), and large areas are utilized for the TFTs, and the TFTs exhibit limited performance.

TFTs thus have limited commercial application and currently are utilized primarily for large area electronics.

Performance enhancements of standard field effect transistor devices are becoming limited with progressive lithographic scaling in conventional applications.

Although various techniques have been developed for substantially controlling nucleation and grain growth processes of semiconductor materials, grain orientation control is lacking.

Further, the post-anneal treatment utilized in conjunction with MILC can be unsuitable in applications in which a low thermal budget is desired.

Images