No-carry multiplication device and processing method thereof

A non-carry, multiplication technology, applied in the field of microelectronics, can solve the problem that the multiplication unit cannot be applied to a non-carry multiplication operation

Active Publication Date: 2012-02-22
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] While having better performance, the above techniques will generate or increase carry
Therefore, the current multiplication unit is completely unsuitable for a carry-less multiplication operation

Method used

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  • No-carry multiplication device and processing method thereof
  • No-carry multiplication device and processing method thereof
  • No-carry multiplication device and processing method thereof

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Embodiment Construction

[0050] Those skilled in the art can manufacture and use the present invention within the scope and requirements of a specific application according to the following content. In addition, those skilled in the art can also make slight modifications according to the following content, and then derive other embodiments. Therefore, the present invention is not limited to the specific embodiments described below, but the broadest scope of the invention is consistent with the principles and novel features.

[0051] In view of the background discussion of multiplication and carryless multiplication above, and the techniques used by processors to generate multiplication results, the Figure 1-3 illustrate. Next, there will be Figure 4-7 Describe how the present invention utilizes the hardware architecture that originally performs general multiplication operations to perform multiplication without carry.

[0052] figure 1 is a possible implementation of a 64-bit multiply unit. The...

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Abstract

The invention provides a no-carry multiplication device and a processing method thereof. The device includes a no-carry pre-format unit, a Booth encoder, a reducer, a left shift device and an XOR gate. The no-carry pre-format unit receives a multiplier operand and formats the multiplier operand into multiple parts. The Booth encoder receives and judges the parts, and selects multiple first part product of a multiplicand operand. By using the parts, multiple second part product of the multiplicand operand can be avoided to select. The second part product causes carry bit. The reducer couples with the Booth encoder. The first part product is totalized through a plurality of carry storage summators. The carry storage summators generate a plurality of totaling bits and a plurality of carry bits. The carry storage summators are arranged in a Wallace tree architecture. When a no-carry multiplying is in execution, the carry bits can not be enabled. The left shift device couples with the reducer and shifts output of the reducer at least one bit. The XOR gate couples with the reducer and the left shift device for XOR operation and generates a no-carry multiplication result.

Description

technical field [0001] The invention relates to a microelectronic technology, in particular to a technology for carrying out multiplication without carry. Background technique [0002] In most of the current communications, the communication data can be encrypted. Valid encryption methods range from simple authentication to hashed encoded messages using symmetric key encryption. In the symmetric key encryption technology, a more common operation mode is Galois Counter Mode (Galois / Counter Mode; hereinafter referred to as GCM). GCM can encrypt and authenticate a message. [0003] Those skilled in the art know that GCM combines the encryption technology of the counter mode and the authentication technology of the recently developed Galois mode. In GCM, the multiplication operation of Galois field is used for authentication. Although the multiplication operation of the Galois field is not within the scope of this case, the multiplication operation of the Galois field is a c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/52
Inventor 提摩西.A.伊里亚德
Owner VIA TECH INC
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