Digital logic operation method and circuit and FPGA chip

A technology of digital logic and arithmetic circuits, applied in electrical digital data processing, digital data processing components, calculations, etc., can solve the problems of large delay, long cycle, low system operation rate, etc., to reduce delay and operation. Period, the effect of reducing the maximum delay

CN108255463AActive Publication Date: 2018-07-06SHENZHEN PANGO MICROSYST CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
Publication Date
2018-07-06

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Abstract

The invention provides a digital logic operation method and circuit and an FPGA chip. A first pipeline register is arranged in a multiplication unit to shorten the time delay between two registers; the circuit comprises an input unit, the multiplication unit and an output unit which are sequentially connected, the input unit includes multiple input registers for receiving input data separately, the multiplication unit includes an encoder, a Wallace tree structure module and an adder which are sequentially connected, the first pipeline register is arranged between any two devices in the multiplication unit, and a second pipeline register is arranged behind the adder; the output unit includes an accumulator and an output register which are connected sequentially, and the output of the accumulator and the output of the multiplication unit are used as the input of the accumulator. By means of the digital logic operation method and circuit and the FPGA chip, the time delay between the firstpipeline register and the second pipeline register is shortened, the maximum time delay of the overall digital logic operation circuit is shortened, the running period of a system is shortened accordingly, and the operation rate of the system is increased.
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Description

technical field

[0001] The invention relates to the technical field of FPGA devices, in particular to a digital logic operation method, a circuit and an FPGA chip. Background technique

[0002] The digital logic operation unit, or DSP, is an important part of the FPGA chip and has a wide range of applications in digital systems. It is indispensable for FPGAs to perform high-speed calculations, especially signal processing. Especially in high-performance microprocessors, digital signal processors, graphics and image systems, scientific computing, and some specific data processing equipment, it is an indispensable part and plays a pivotal role. The performance of DSP often becomes a factor in the system performance bottleneck. In DSP, the multiplier is an important digital module in DSP. Now basically all multipliers use booth structure multipliers, which are composed of encoders, wallance tree structures and adders. Please refer to figure 1 , figure 1 Shows a block diagram...

Examples

no. 1 example

[0030] Please refer to image 3 , image 3 It is a schematic circuit structure diagram of a digital logic operation circuit provided by the first embodiment of the present invention, including an input unit 31, a multiplication unit 32 and an output unit 33 connected in sequence;

[0031] The input unit 31 includes several input registers 311 for receiving input data respectively;

[0032] The multiplication unit 32 comprises an encoder 321, a Wallace tree structure module 322 and an adder 323 connected in sequence, the first pipeline register 324 is arranged between any two devices in the multiplication unit 32, and the second pipeline register 325 is arranged in the adder after 323;

[0033] The output unit 33 includes an accumulator 331 and an output register 332 connected in sequence, and the output of the accumulator 331 and the output of the multiplication unit 32 serve as the input of the accumulator 331 .

[0034] The digital logic operation circuit in the present e...

no. 2 example

[0045] Please refer to Figure 5 , Figure 5 A flow chart of a digital logic operation method provided in the second embodiment of the present invention, including:

[0046] S501. The input register in the output unit receives input data;

[0047] S502. The input data is input to the multiplication unit, and the multiplication operation is performed through the encoder, the Wallace tree structure module and the adder in the multiplication unit in turn to obtain the operation data; wherein, a second device is set between any two devices in the multiplication unit. A water register is provided with a second water register after the adder;

[0048] S503. An operation data input and output unit, the output unit includes an accumulator and an output register connected in sequence, and the output of the accumulator and the output of the multiplication unit are used as the input of the accumulator.

[0049] The digital logic operation circuit in this embodiment roughly includes th...