Digital logic operation method and circuit and FPGA chip

Abstract

The invention provides a digital logic operation method and circuit and an FPGA chip. A first pipeline register is arranged in a multiplication unit to shorten the time delay between two registers; the circuit comprises an input unit, the multiplication unit and an output unit which are sequentially connected, the input unit includes multiple input registers for receiving input data separately, the multiplication unit includes an encoder, a Wallace tree structure module and an adder which are sequentially connected, the first pipeline register is arranged between any two devices in the multiplication unit, and a second pipeline register is arranged behind the adder; the output unit includes an accumulator and an output register which are connected sequentially, and the output of the accumulator and the output of the multiplication unit are used as the input of the accumulator. By means of the digital logic operation method and circuit and the FPGA chip, the time delay between the firstpipeline register and the second pipeline register is shortened, the maximum time delay of the overall digital logic operation circuit is shortened, the running period of a system is shortened accordingly, and the operation rate of the system is increased.

Description

technical field [0001] The invention relates to the technical field of FPGA devices, in particular to a digital logic operation method, a circuit and an FPGA chip. Background technique [0002] The digital logic operation unit, or DSP, is an important part of the FPGA chip and has a wide range of applications in digital systems. It is indispensable for FPGAs to perform high-speed calculations, especially signal processing. Especially in high-performance microprocessors, digital signal processors, graphics and image systems, scientific computing, and some specific data processing equipment, it is an indispensable part and plays a pivotal role. The performance of DSP often becomes a factor in the system performance bottleneck. In DSP, the multiplier is an important digital module in DSP. Now basically all multipliers use booth structure multipliers, which are composed of encoders, wallance tree structures and adders. Please refer to figure 1 , figure 1 Shows a block diagram...

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Problems solved by technology

[0003] The invention provides a digital logic operation method, circuit and FPGA chip, aiming to solve the problems of large delay, long cycle and low system operation rate in the digital logic operation circuit in the prior art

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