Multi-input shift summation accumulator based on Wallace tree

Abstract

The invention belongs to the technical field of intelligent processors, and particularly provides a multiple-input shift summation accumulator based on a Wallace tree, which comprises an exclusive-OR gate array, an initial carry vector generation module, a Wallace compression tree, a 4-2 compressor, an accumulation register and an adder, through the exclusive-OR gate array and the initial carry vector generation module, the original code and subtraction operation are converted into complement addition at one time to be used for a Wallace tree, native support for multiple data formats and addition and subtraction is provided, and hardware overhead is saved; and then accumulation is realized based on a 4-2 compressor and an accumulation register, the 4-2 compressor compresses two output values of the Wallace tree and a storage value in the accumulation register to obtain two intermediate results, and the intermediate results are output to the accumulation register to update the storage value, so that the carry chain overhead for summation of the results of the Wallace tree is saved, and meanwhile, a full adder carry chain is removed before the accumulation register. The design of an assembly line is greatly facilitated, and the clock frequency and the accumulation efficiency can be improved.

Description

technical field [0001] The invention belongs to the technical field of intelligent processors, relates to a multi-input accumulator, and specifically provides a Wallace tree-based multi-input shift summation accumulator which is convenient for designing pipelines and supports original code format and subtraction. Background technique [0002] Pipelining is a technology to improve hardware throughput. By inserting pipeline registers at appropriate positions in the circuit, the clock frequency can be increased and the amount of data processed can be increased. The original code format is a data format that uses symbols and absolute values ​​to represent values. It is a numerical representation method used in floating-point format; this data format often uses the highest weight bit as the sign bit, and the remaining bits represent absolute values. The sign bit 0 is Positive, 1 is negative. The Wallace tree is a circuit structure that quickly sums multiple inputs. This structur...

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Problems solved by technology

The design of the shift summation accumulator based on the Wallac e tree is mainly aimed at the summation operation in the complement format. When the original code or subtraction is involved, it is necessary to convert the original code or subtrahend into the corresponding complement, and then perform Shift-sum-accumulate operation; existing structures such as figure 1 As shown, when processing large-bit-width data, it is necessary to convert the input data into complement codes for operation, such as figure 1 As shown in the dotted line box 1, the complement code conversion requires a large adder to complete, such as multiple sets of full adder carry chains, the circuit area is large, and the circuit delay cannot be ignored; at the same time, when it comes to pipeline design, this structure The partial sum of a set of data is obtained first through the Wallace tree cascade adder, and then accumulated through subsequent independent accumulators, such as figure 1 As shown in the dotted box 2, the whole structure needs two adders to perform operations. When processing large-bit-width data, it is difficult to control the circuit clock and pipeline design

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