A testing method for a second-order booth coded wallace tree multiplier circuit

Abstract

The present invention relates to a test method for a second-order Booth coded Wallace tree multiplier circuit: S1, obtaining the multiplier structure; S2, generating a test vector set for testing a partial product generation circuit; S3, generating a test vector set for a partial product compression circuit Test vector set: traverse all inputs of all compressor units in the partial product compression circuit to obtain a set of partial product array outputs; according to the topology of the multiplier, convert each partial product array output in the set of partial product array outputs into The original input of the multiplier, thereby obtains the test vector set that is used for testing partial product compression circuit; S4, compares the test vector used for partial product generation circuit and partial product compression circuit, removes repeated test vectors, obtains final test vector set input to the multiplier for test verification; S5, using a pseudo-random code test method to test the final summation circuit part. The present invention uses fewer test vectors to achieve higher test coverage.

Description

technical field [0001] The invention relates to a test method for a multiplier circuit, in particular to a test method for a Wallace tree multiplier circuit of second-order Booth coding, and belongs to the field of integrated circuits. Background technique [0002] Multipliers are widely integrated in digital signal processors and microprocessors to meet the needs of high-speed multiplication operations. In order to achieve high-speed multiplication, the design principle of the multiplier mainly adopts a method similar to manual multiplication, that is, all partial products are generated at the same time, and the partial products are compressed and finally summed to obtain the product. Based on this, the multiplier circuit mainly includes three parts: a partial product generation circuit, a partial product compression circuit, and a final summation circuit. [0003] At present, the partial product generating circuit of the mainstream multiplier mainly adopts the second-orde...

AI Technical Summary

Problems solved by technology

[0004] The Wallace tree multiplier of the second-order Booth code has a large bit width, which is difficult to test by traversal

But its disadvantages are: using circular vectors, it is necessary to traverse all input situations under a certain cycle length, and the test vector set is still large, resulting in a long test time

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