Clock phase-locked method to extract synchronous clock of global positioning system and clock phase-locked loop

Abstract

The invention discloses a synchronous clock phase-locking method for extracting synchronous clock of global positioning system. The invention is used for capturing test signals from global positioning system module with a output frequency ranging of 500Hz to 1MHz, capturing compared clock signals synchronous with the local clock signals, detecting phase of the test signals and the compared clock signals, and adjusting the frequency of local clock signal according to the phase detection results so that the compared clock signals are synchronous with the test signals. By adopting the method, the clock phase-locking ring disclosed by the invention can quickly lock the synchronous clock of the global positioning system. The invention adopts the high-frequency clock signals as the reference clock, thereby reducing the difficulty in designing the frequency division circuit, shortening the phase-locking time of the clock phase-locking ring and saving a large quantity of hardware resources.

Description

technical field [0001] The invention relates to a clock synchronization technology in the communication field, in particular to a clock phase-locked method for extracting a global positioning system synchronous clock and a clock phase-locked loop. Background technique [0002] The clock synchronization system is used to provide a synchronous clock for the digital communication network, and the clock synchronization is the basis for mutual communication between various devices in the digital communication network. If there is no good clock synchronization, bit errors and code slips will inevitably occur during the transmission of digital information, resulting in a decline in communication quality. For example, there are clicking sounds during voice calls, incomplete information in fax services, increased packet loss rate in data services, and blurred transmitted images. In order to ensure the quality of service, a clock synchronization system is essential in a communication...

AI Technical Summary

Problems solved by technology

The f0 compared by the phase detector 11 is the second pulse signal. Since the second pulse signal has a large period, the phase-locking time is long, and the phase-locked loop needs a long time to enter a stable state.

At the same time, since the frequency division multiple N of tens of megahertz signals output by the voltage-controlled oscillator 13 to 1 Hz is tens of trillion times, the value of N is very large, and the realization of the frequency division circuit needs to consume a large amount of system logic. At the same time, it also increases the difficulty in the design of the frequency division circuit, which can easily lead to glitches in the frequency-divided signal, which in turn leads to the disadvantages of complex clock phase-locked loop circuit structure, reduced reliability, and increased cost.

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