Frequency divider monitor of phase lock loop

a technology of phase lock loop and frequency divider, which is applied in the direction of automatic control, electrical equipment, etc., can solve the problems of inability to supply clock signals to the integrated circuit or electronic system that supplies the clock signal, and frequency dividers are one of the most prone to failur

Inactive Publication Date: 2008-03-20
FENG KAI +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Frequency dividers are one of the most prone to failure components of the high speed phase lock loops.
In such a case, the integrated circuit or electronic system to which the clock signal is supplied can malfunction.

Method used

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  • Frequency divider monitor of phase lock loop
  • Frequency divider monitor of phase lock loop
  • Frequency divider monitor of phase lock loop

Examples

Experimental program
Comparison scheme
Effect test

first embodiment

[0023]FIG. 1 is the block circuit diagram of a first frequency generator and monitor circuit 100A according to the present invention. In FIG. 1, frequency generator and monitor circuit 100A includes a phase locked loop circuit which includes a phase detector 105, a charge pump 110, a voltage controlled oscillator 115 which generates a clock signal fVCOO, a forward frequency divider 120 (which is optional) which generates a clock signal fOUT and a feedback frequency divider 125 which generates a clock signal fB.

[0024] A first input of phase detector 105 is connected to clock signal fIN and a second input of the phase detector is connected to an output (fB) of feedback frequency divider 125. An output of phase detector 105 is connected to an input of charge pump 110. An output of charge pump 110 is connected to and input of voltage controlled oscillator 115. An output (fVCOO) of voltage controlled oscillator 115 is connected to an input of forward frequency divider 120 and an input of...

second embodiment

[0031]FIG. 2 is block circuit diagram of a second frequency generator and monitor circuit 110B according to the present invention. Frequency generator and monitor circuit 110B is similar to frequency generator and monitor circuit 110A (see FIG. 1) except the input of feedback frequency divider 125 is connected to the output of forward frequency divider 120 instead of the output of voltage controlled oscillator 115 (see FIG. 1).

[0032] Operation of frequency generator and monitor circuit 110B is similar to the operation of frequency generator and monitor circuit 110A (see FIG. 1), but because the output (fVCOO) of forward frequency divider 120 is presented to the input of feedback frequency divider 125, the value R includes the divide ratio of forward frequency divider 120 and the divide ratio of feedback frequency divider 125. So both forward frequency divider 120 and feedback frequency divider 125 are monitored by frequency divider monitor 130.

third embodiment

[0033]FIG. 3 is block circuit diagram of a third frequency generator and monitor circuit 110C according to the present invention. Frequency generator and monitor circuit 110C is similar to frequency generator and monitor circuit 110B (see FIG. 2) except the input of feedback frequency divider 125 is connected to the output of external frequency divider 170 instead of to the output of forward frequency divider 120 (see FIG. 2) and the input of external frequency divider 170 is connected to the output of forward frequency divider 120.

[0034] Operation of frequency generator and monitor circuit 110B is similar to the operation of frequency generator and monitor circuit 110B (see FIG. 2), but because the output (fVCOO) of forward frequency divider 120 is presented to the input of forward frequency divider 120, the output (fOUT) of forward frequency 120 is presented to the input of external frequency divider 170 and the output (fEXT) of external frequency divider 170 is presented to the i...

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PUM

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Abstract

A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.

Description

RELATED APPLICATIONS [0001] This application is a continuation of and claims priority of copending U.S. patent application Ser. No. 11 / 276,410 filed on Feb. 28, 2006.FIELD OF THE INVENTION [0002] The present invention relates to the field of frequency divider circuits; more specifically, it relates to methods and circuits for monitoring the operation frequency of the divider circuits. BACKGROUND OF THE INVENTION [0003] In modern integrated circuits and electronic systems, clock signals are generated using phase lock loop circuits that use frequency feedback to generate a clock signal with stable frequency value and constant phase performance. Frequency dividers are one of the most prone to failure components of the high speed phase lock loops. In one failure mode, the output frequency of the frequency divider changes from design or drifts. In such a case, the integrated circuit or electronic system to which the clock signal is supplied can malfunction. Therefore, there is a need for...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H03L7/08
CPCH03L7/18H03L7/02
Inventor FENG, KAIJIN, ZHENRONG
Owner FENG KAI
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