44results about How to "Constant bandwidth" patented technology

Aspects of the present invention relate to providing see-through computer display optics and reduction of color breakup in presented content.

Aspects of the present invention relate to providing see-through computer display optics and reduction of color breakup in presented content.

Aspects of the present invention relate to providing see-through computer display optics and reduction of color breakup in presented content.

The present invention facilitates clock and data recovery (330,716/718) for serial data streams (317,715) by providing a mechanism that can be employed to maintain a fixed tracking capability of an interpolator based CDR circuit (300,700) at multiple data rates (e.g., 800). The present invention further provides a wide data rate range CDR circuit (300,700), yet uses an interpolator design optimized for a fixed frequency. The invention employs a rate programmable divider circuit (606,656,706) that operates over a wide range of clock and data rates (e.g., 800) to provide various phase correction step sizes (e.g., 800) at a fixed VCO clock frequency. The divider (606,656,706) and a finite state machine (FSM) (612,662,712) of the exemplary CDR circuit (600,650,700) are manually programmed based on the data rate (614,667). Alternately, the data rate may be detected from a recovered serial data stream (718) during CDR operations (on-the-fly) utilizing a frequency detection circuit (725) to automatically program the divider (706) and FSM (712) to provide CDR circuit operation at the nearest base clock rate (716).

A method and apparatus for bandwidth reservation for data flows in interconnection networks. Some embodiments of an apparatus for transmitting a data stream include a transmitter to transmit a data stream to a recipient apparatus, the data stream including a plurality of data packets. The apparatus further includes a receiver to receive a response from the recipient apparatus regarding data packet arrival status, and a network unit to direct the operation of the transmitter, the network unit to direct the transmitter to maintain the data stream with a constant bandwidth.

The present invention provides a radar altimeter system with a closed loop modulation for generating more accurate radar altimeter values. The system includes an antenna, a circulator, a receiver, and a transmitter. The circulator receives or sends a radar signal from/to the antenna. The receiver receives the received radar signal via the circulator. The transmitter generates a radar signal and includes a phase-locked loop circuit for generating the radar signal based on a pre-defined phase signal. The transmitter includes a direct digital synthesizer that generates the phase signal based on a pre-defined clock signal and a control signal. The system includes a digital signal processor and a tail strike warning processor that determine position of a tail of the aircraft relative to ground and present an alert if a warning condition exists based on the determined position of the tail of the aircraft and a predefined threshold.

In one embodiment, a set of tracking filters to be coupled between an amplifier and a mixer is provided. The tracking filters may be differently configured depending on band of operation. For example, a first set of the filters can be configured to maintain a substantially constant Q value across their operating bandwidth while a second set of the filters can be configured to maintain a substantially constant bandwidth across their operating bandwidth.

A tunable inductor arrangement arrangable on a chip or substrate is disclosed. The tunable inductor comprises a first winding part connected at one end to a first input of the tunable inductor arrangement, a second winding part connected at one end to the other end of the first winding part, a third winding part connected at one end to a second input of the tunable inductor arrangement, a fourth winding part connected at one end to the other end of the third winding part, and a switch arrangement arranged to tune the tunable inductor arrangement. Tuning is performed by selectively provide any of a circuit comprising the first and third winding parts in series between the first and second inputs, or a circuit comprising the first, second, fourth and third winding parts in series between the first and second inputs. The first and third winding parts are arranged on the chip or substrate such that magnetic fields of the first and third windings are essentially common, and the second and fourth winding parts are arranged to cancel electro-magnetic coupling with the first and third winding parts. A receiver, a transceiver, a communication device, a method and a computer program are also disclosed.

The invention provides a programmable complex filter, a GNSS system chip and a radio frequency receiver. The programmable complex filter supports a zero intermediate frequency mode and a low intermediate frequency mode. The programmable complex filter comprises a trans-impedance amplifier module, a complex filter module and an RC calibration module. The trans-impedance amplifier module converts the intermediate frequency differential current signal into a noise intermediate frequency differential voltage signal; The complex filter module is used for filtering interference signals in the noise intermediate frequency differential voltage signals, so that the intermediate frequency differential voltage signals can be output in a zero intermediate frequency mode or a low intermediate frequency mode; the RC calibration module comprises an analog processing unit and a digital processing unit and is used for controlling the switching state of the resistance-capacitance array unit according to the switching signal and the clock signal; when the switch state is closed, the programmable complex filter supports a low-intermediate frequency mode; when the switch state is off, the programmable complex filter supports a zero intermediate frequency mode. The invention has the characteristics of high integration level and flexible and configurable mode.

The invention discloses a constant-bandwidth broadband filter with an electrically-adjusted transmission zero point. The constant-bandwidth broadband filter comprises a micro-strip dielectric substrate (1), a metal grounding plate (2), a short-circuit branch loading resonator (3), a coupling feeder line (4), a grounding hole (5), a capacitance variable diode (6) and a DC biasing circuit (7). A folded short-circuit branch loading resonator is adopted to increase a current path, the resonance frequency is reduced, and a folding double-feeder structure is loaded on the inner side, so that the broadband filter is compact in structure and small in size. A capacitance variable diode control source is coupled with a load, and the capacitance value of the capacitance variable diode is adjusted through a direct current bias circuit, so that the position and the quantity of transmission zero points are changed, and the selective performance of the broadband filter is improved. The performance ofthe passband is not affected, and the constant bandwidth is kept, so that the performance stability of the filter is ensured.

The embodiment of the invention discloses a high-energy-efficiency equalizer architecture. The architecture comprises a filtering module which is used for filtering an input signal, a processing module which is connected with the filtering module, the processing module comprises a plurality of MOS tubes which are in complementary connection, and the processing module is used for transconductance amplification of a current signal of the input signal; and the architecture further comprises a conversion module which is connected with the processing module, and the conversion module is used for converting the current signal into a voltage signal. According to the high-energy-efficiency equalizer architecture provided by the embodiment of the invention, by accessing a complementary transconductance tube and using the same transconductance amplification stage current, double transconductance can be obtained, and meanwhile, the output transresistance stage can still keep constant bandwidth and gain, so that compared with a traditional linear equalizer architecture, the high-energy-efficiency equalizer architecture achieves the effects of high compensation capability and high driving capability.

The invention discloses a digital control variable gain amplifier, which comprises three stages of VGA circuits and an output buffer circuit. The first stage and the second stage of the three stages of VGA circuits are composed of a variable transconductance amplifier and a constant trans-impedance amplifier. The third stage is composed of a variable transconductance amplifier and a variable trans-impedance amplifier, a high-pass filter is adopted between the two stages of VGA circuits to eliminate direct-current bias voltage generated by each VGA unit, the reliability of the circuits is guaranteed, and an output buffer is used for driving 100-ohm differential load impedance. The variable transconductance stage and the variable transimpedance stage are introduced into the three stages of VGA circuits at the same time, so that the problem of mismatching caused by excessive transistors is avoided, high gain, accurate gain step length and constant bandwidth are realized, the linearity isrelatively good, and a wide dynamic range system is realized.

The invention provides a filter. The filter comprises a filter cavity, at least one partition plate and resonant rods, wherein the partition plate is arranged in the filter cavity and is parallel to a side wall of the filter cavity, the filter cavity is partitioned to a plurality of resonant cavities, the resonant rod is arranged in each resonant cavity, the resonant rods are parallel to the partition plate, and coupling windows are formed in two ends of the partition plate and are used for achieving cavity coupling of the filter. In the filter, a coupling adjustment device is not needed to be additionally arranged, and the filter is simple in structure.

The invention discloses a phase-locked loop frequency synthesizer. The phase-locked loop frequency synthesizer comprises a phase frequency detector, a charge pump and an adaptive filter, a Voltage-controlled oscillator, a Frequency divider and a decoder; the phase frequency detector , a charge pump and an adaptive filter, the Voltage-controlled oscillator, the frequency dividers are sequentially connected in series to form a feedback loop; the decoder is connected between the frequency divider and the self-adaptive filter; the decoder is used for decoding the frequency division ratio of the frequency divider and providing a corresponding control signal for the adaptive filter; and the self-adaptive filter comprises a self-adaptive on-resistance network which has different resistance valuesunder the control of the control signal and can keep the loop bandwidth of the phase-locked loop frequency synthesizer constant. The phase-locked loop frequency synthesizer disclosed by the inventionrealizes that the bandwidth of the loop is not changed along with the change of the output frequency, and has better system stability and response speed.