Out-of-order execution micro-processor and method of executing the related command

A technology for microprocessors and executing instructions, applied in the direction of machine execution devices, etc., can solve problems such as system performance damage

Active Publication Date: 2010-11-24
VIA TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The inventors of the present invention observed an additional dependency of a SHF instruction (a generic term for shift instructions) on the nearest older EFLAGS-modified instruction, which is shift-by-zero only It is neces

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  • Out-of-order execution micro-processor and method of executing the related command
  • Out-of-order execution micro-processor and method of executing the related command
  • Out-of-order execution micro-processor and method of executing the related command

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Embodiment Construction

[0028] In order to solve the aforementioned performance problems, the register alias table (RAT) always assumes that the displacement is non-zero. In this way, an SHF instruction does not need to depend on a flag register EFLAGS (that is, There is no need to depend on the nearest flag register EFLAGS-modify command older than the SHF command). If the execution unit later determines that the displacement of the SHF instruction is zero, and encounters an instruction that specifies a condition code result as a source operand, the above instruction depends on the flag of an older SHF instruction When the EFLAGS result is stored in the register, the reorder buffer (ROB) will replay the instructions dependent on the SHF instruction. In one embodiment, the result of the above condition code is, for example, the result of a flag register EFLAGS of the x86 architecture, which may be a value in the flag register EFLAGS.

[0029] See figure 1 , Is a block diagram showing a microprocessor 1...

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Abstract

The invention provides an out-of-order execution micro-processor, comprising a temporary memory surname watch for generating a first indication for indicating whether one command depends on a condition code result of a shift command or not. A micro-processor also comprises a first execution unit for executing the shift command and generating a second indication and the second indication indicateswhether one shift amount of the shift command is zero or not. The micro-processor also comprises a second execution unit for receiving the first indication and the second indication and generating a return signal, thus when the first indication indicates that the command depends on the condition code result of the shift command and the second indication indicates that the shift amount of the shift command is zero, the command is returned.

Description

Technical field [0001] The present invention relates to a microprocessor with an out-of-order execution micro-architecture, and particularly relates to a microprocessor with an x86 architecture. Background technique [0002] The x86 architecture defines that when an x86 displacement instruction (Shift Right (SHR) instruction or ShiftLeft (SHL) instruction, commonly known as Shift (SHF) instruction) has a displacement of zero, the flag register EFLAGS will not change; Otherwise, the bit of the flag register EFLAGS will be updated to reflect the result of the shift operation. However, this may cause the dependency determination of a condition code (CC) instruction after an x86 shift instruction (x86SHF instruction) (that is, the read unit (reader) of the flag register EFLAGS) , Such as jumping condition code (Jcc) / setting condition code (Setcc) / moving condition code Movcc), it causes problems. The following program fragment is used to illustrate such a problem: [0003] ADD EAX, E...

Claims

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Application Information

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IPC IPC(8): G06F9/30
Inventor 吉拉德·M·卡尔泰瑞·派克斯布莱恩·W·伯格马修·D·戴
Owner VIA TECH INC
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