System and method for controlling I2C communication based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a system and a method for controlling I2C communication based on an FPGA (Field Programmable Gate Array). The system and the method are applied to communication between slave equipment and host equipment in a communication system. MCUs (Micro Control Units) of the slave equipment are connected with the FPGA through main control I2C modules, and an FPGA unit is constructed by programming. The FPGA unit comprises the main control IC2 modules, a control module and a first storage module, wherein the main control I2C modules are connected with the control module and the first storage module respectively; the main control I2C modules comprise a leading flag register, a clock register, a data length register, a read-write flag register, an address register, a write register, a read register, a continuous read-write flag register and a continuous data length register. In the I2C modules provided by the invention, nine special registers are designed for realizing read-write functions, so that high flexibility and portability are achieved, one-time reading and writing operation can be realized, and read operation and write operation can be implemented separately.

Description

technical field [0001] The invention belongs to the field of communication control, and relates to a system and method for controlling I2C communication based on FPGA. Background technique [0002] With the rapid development of communication technology, sensor technology, embedded operation technology and microelectronics technology, the integration of smart products is getting higher and higher, so the communication speed requirements of the board-level circuit of the product are also increasing. As a basic communication method between chips, the I2C protocol is widely used in electronic devices. Therefore, improving the communication speed of I2C between devices is crucial to improving the system speed. [0003] At present, when researchers design the system, they connect the master device of the customized circuit and the slave devices with a limited number of I2C interfaces. The master device with only one I2C interface can only communicate with multiple I2C slave devic...

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Problems solved by technology

[0003] At present, when researchers design the system, they connect the master device of the customized circuit and the slave devices with a limited number of I2C interfaces. The master device with only one I2C interface can only communicate with multiple I2C slave devices in turn. When an I2C slave device communicates, other devices need to wait, which greatly reduces the efficiency of communication between devices. Secondly, the I2C bus protocol stipulates that the number of slave devices mounted on an I2C bus is limited. Therefore, The master device is connected with multiple slave devices through a single I2C bus, which cannot meet the requirements of high-speed communication

[0004] As a semi-custom circuit in the field of ASIC application specific integrated circuits, FPGA has brought changes to the existing custom circuit technology with slow speed and poor performance due to its advantages of high flexibility, reconfigurability, high speed and abundant resources. FPGA has abundant resources to program and reconfigure the I2C interface of the master control and the I2C interface of multiple slave devices, which can realize simultaneous interactive communication between the CPU and peripherals. However, as devices using I2C channels, they require different communication methods. Similarly, some devices can only perform reading or writing in one operation, while some devices require reading and writing to be completed in one operation. The current application is only designed according to the timing requirements of the slave device.

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