Multi-core processor control method

Abstract

The load / sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality product chips at time of semiconductor production, by equipping a core selection flag register that maintains the status of each core, and controlling the output to the core block from the processor common block through that core selection flag register status.

Description

CROSS REFERENCE TO RELATED APPLICATION [0001] This application is related to and claims priority to Japanese Application No. 2004-176619, filed Jun. 15, 2004 in the Japanese Patent Office, the contents of which are incorporated by reference herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention is related to processor control methods of multiple execution processing cores (“cores”) of CPUs (Central Processing Units), MPUs (Micro Processing Units), DSPs (Digital Signal Processors), and GPUs (Graphics Processing Units, or graphic processing LSIs, or geometry engines), etc., or other applicable processors. [0004] 2. Description of the Related Art [0005] Conventionally, computer systems such as servers that demand particularly high processing abilities such as mission-critical processing for enterprises have improved their processing ability by connecting to multiple processors by being structured using a loosely coupled cluster structure, or a...

AI Technical Summary

Benefits of technology

[0034] The present invention, for processors that are CMP, etc. with a multi-core structure, has the objective of equipping core selection flag registers that maintain each core's status, and through the status of these core selection flag registers, the output from the processor common blocks to the core blocks are controlled, and a flexible core settings method can be supported, thus actualizing the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield through the relief of partial core quality chips during semiconductor production.

Problems solved by technology

However, for loosely coupled cluster structures the communication overhead between server nodes is an issue, and for tightly coupled SMP structures the complexity of server hardware is an issue, so either case has limitations regarding the improvement of performance for singular computer systems using current architecture.

However, in the case of a multi-core structure such as that of a CMP, etc., in exchange for the improvement of processing performance through an increase in core numbers, problems such as complication of controls by implementing multiple cores and a decrease in yield during semiconductor production due to the increase in die size have occurred.

In particular, the decrease in yield during semiconductor production due to the increase in die size is a very important issue for multi-core processors that use multi-cores such as CMPs, etc.

In this conventional structure number 1, since only the same load data can be set to CORE-0 setup register 419 and CORE-1 setup register 420, there was a problem of being unable to set individual settings on each core.

Due to this, there has been an issue of difficult applicability, since multi-core control logic must become large-scale for large-scale multi-core processors that are likely to become mainstream in the future.

Due to this, there has been an issue of difficult applicability, since decode logic must become large-scale for large-scale multi-core processors that are likely to become mainstream in the future.

As described above, conventional technology of processors with multi-core structures through CMP, etc., has problems such as complication of controls for multiple cores and a decrease of yield due to an increase in die size.

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