939 results about "Semiconductor production" patented technology

Heater module, and semiconductor manufacturing equipment in which the heater module is utilized, for raising the cooling speed of a post-heating heater markedly more than conventional, and that can contribute toward bettering and improving productivity, without accompanying scaling-up of and cost increases in the semiconductor manufacturing equipment. The heater module is furnished with heater part 1a for controlled heating of a wafer placed on its top face, and block part 3a provided to be shiftable relative to said heater part, for varying heat capacity in total with heater part 1a by abutting on or separating from the reverse surface of heater part 1a. By having the heat capacity of block part 3a be 20% or more of the total heat capacity of heater part 1a and block part 3a, the heater cooling speed can be made 10° C./min or more.

A semiconductor production system has a semiconductor manufacturing apparatus having an exposure unit, a control unit for controlling the exposure unit and a storage device; a semiconductor inspection apparatus having an observation unit, a control unit for controlling the observation unit and a storage device; and a storage device commonly used by the semiconductor manufacturing apparatus and the semiconductor inspection apparatus. The manufacturing apparatus, the inspection apparatus and the commonly used storage device are interconnected via a storage area network. With the semiconductor manufacturing apparatus and the storage device linked together via the storage area network, a large volume of image data or design data can be communicated at high speed, thus improving the system throughput.

A method and system for efficient allocation of limited manufacturing resources over time to meet customer demand. At the enterprise planning level this typically requires determination of a feasible production schedule for an extended supply chain. The method and system utilizes a new and unique type of systematic decomposition based on both product and process considerations. This approach simultaneously reduces the model size (and therefore computation time) and increases modeling flexibility from strictly linear programming based decision making to include more general nonlinear programming characteristics.

A heating apparatus for a semiconductor producing system is provided, including a heater having a mounting face, an opposed back face, a first resistance heating element, a second resistance heating element provided along substantially the same plane as the first heating element, a first terminal connected with the first heating element and a second terminal connected with the second heating element. A supporting member is fixed to the back face of the heater. First and second power supply means are respectively connected with the first and second terminals and contained in an inner space of the supporting member. A conductive connector connects the first heating element and the first terminal but not the second heating element. The first heating element is provided in a first zone, the second heating element is provided in a second zone, and the conductive connector is provided in the plane and the second zone.

It is an object of the present invention to provide a semiconductor device production method in which an electroconductive capping (metal) layer is formed on a copper interconnect surface, wherein the capping (metal) layer is selectively formed to produce the semiconductor device of high reliability. In the semiconductor device production method, a capping (metal) layer is formed on a copper interconnect in a semiconductor integrated circuit, a first capping (metal) layer is formed by electroless plating with a plating solution containing a reducing agent active on a copper interconnect surface, and then a second capping (metal) layer is formed by another electroless plating.

In a method of manufacturing a semiconductor, in which a semiconductor substrate is worked/treated in each manufacturing step of a semiconductor manufacturing line, image data is acquired before and after working/treating the semiconductor substrate transported into a manufacturing apparatus disposed in each manufacturing step, respectively, defects attributed to treatment conditions of the manufacturing apparatus are detected from the image data before the working/treating, or non-defective master image data, and the image data after the working/treating, and the treatment conditions of the manufacturing apparatus are changed/controlled based on the detection result to work/treat the semiconductor substrate.

The invention provides an optimized scheduling method of a semiconductor production line based on a Petri net and immune algorithm. The method utilizes the Petri net for carrying out modeling to the semiconductor production line, comprising a path scheduling model, an equipment group scheduling model and an equipment scheduling model; and the immune algorithm is embedded in the Petri net model as the scheduling strategy. By the Petri net model, all possible acts of the semiconductor manufacturing system can be described, such as work-piece processing, equipment failure, batch processing, defected wafer rework and the like. The chromosome of the immune algorithm can be directly structured out of search nodes of the Petri net model, and each gene of each chromosome records the scheduling strategy of each equipment group. A better chromosome is obtained by the simulation of the Petri net model, and therefore a sub-optimal scheduling strategy is generated. The optimized scheduling method has the advantages of reducing the complexity of the model and improving the reusability of the model and the scheduling algorithm.

The load/sense control of the setting value that corresponds to the processor core for CMP, etc. processors that have multi-cores realize, for such processors with multi-core structures, the shortening of system boot time during multi-core operation, flexible debugging methods, and improvement of yield with the aid of partial core quality product chips at time of semiconductor production, by equipping a core selection flag register that maintains the status of each core, and controlling the output to the core block from the processor common block through that core selection flag register status.

The invention relates to a semiconductor production line self-adaptation dynamic dispatching device which is connected with a manufacturing execution system. The dispatching device comprises a dispatching management device, a learning device and a display device. The dispatching management device is connected with the manufacturing execution system, and the dispatching management device, the learning device and the display device are connected in sequence. The dispatching management device acquires a list of current workpieces to be dispatched through the manufacturing execution system and transmits the list of the current workpieces to be dispatched to the learning device, the learning device calculates machining priorities of the current workpieces to be dispatched according to a dispatching rule stored in the learning device and transmits the priorities of the current workpieces to be dispatched to the display device, and the display device displays the priorities of the current workpieces to be dispatched. Compared with the prior art, the semiconductor production line self-adaptation dynamic dispatching device has the advantages of being capable of improving workpiece machining efficiency and bottleneck equipment use ratios, good in dynamic regulation performance, and the like.

The invention relates to a scheduling method for a semiconductor production line based on multi-ant-colony optimization. The method comprises the following steps of: determining bottleneck processing areas of the semiconductor production line, wherein processing areas, of which average utilization rate exceeds 70 percent, of equipment are regarded as the bottleneck processing areas; setting the number of ant colonies as the number of the bottleneck processing areas, and initializing a multi-ant-colony system; parallelly searching scheduling schemes of all bottleneck processing areas by all ant colony systems; restraining and integrating the scheduling schemes of all bottleneck processing areas into one scheduling scheme for all bottleneck processing areas according to a procedure processing sequence, and deducing the scheduling schemes of other non-bottleneck processing areas by using the scheduling scheme and the procedure processing sequence as restraint to obtain the scheduling scheme of the whole semiconductor production line; and judging whether program ending conditions are met, if so, inputting the scheduling scheme which is optimal in performance, otherwise, updating pheromones of the ant colonies by using the scheduling scheme which is current optimal in performance, and guiding a new round of searching process. The method has the advantages that: an important practical value is provided for solving the optimal dispatching problem of the semiconductor production line; and important instructional significance is provided for improving the production management level of semiconductor enterprises of China.

The invention discloses a performance prediction method applicable to dynamic scheduling for a semiconductor production line. An extreme learning machine (ELM) is applied to prediction and modeling in the performance prediction method. Feeding control and scheduling rules are considered in a unified manner in the method, short-term scheduling key performance indexes such as an equipment utilization rate and a movement step number are predicted on the basis of a real-time state of a system, and a foundation is provided for dynamic real-time scheduling. A novel feed-forward neural network of the ELM is introduced into the semiconductor manufacturing system, and a prediction model is built by the aid of available data of the production line. As shown by test results, ideal prediction results can be quickly acquired by the method implemented by the aid of the ELM, the method has obvious advantages and an obvious application prospect in the aspects of parameter selection and learning speed as compared with the traditional neural network modeling method, and a new idea is provided for online optimal control.

An improved crosspoint memory array device comprising a plurality of memory cells, each memory cell being disposed at an intersection region of bit and word conductive lines, electrically coupled to one of the first conductive lines at a first terminal and to one of the second conductive lines at a second terminal, and comprising a controllable electrical resistance, wherein a back to back Schottky diode is located between each memory cell and one of the said conductive lines, and wherein each conductive line is electrically coupled to at least two thin film transistors (TFTs). The device is substantially produced in BEOL facilities without need of front end semiconductor production facilities, yet can be made with ultra high density and low cost.

The invention discloses a dynamic dispatching method on the base of pheromone in semi-conductive product line, which comprises the following steps: first, storing pheromone variation of each WIP which relates to the WIP delivery date, holding time of waiting processing equipment, pure processing time and production periodic multiplication factor; second, storing pheromone variation which relates to equipment load; then, integrating the WIP pheromone variation and relating equipment pheromone variation, generating a selective variation of each WIP; finally, elaborating them on the equipment according to the method which consists of short-term and long-term function index to improve multi-function index production or making system.

The invention discloses a graphite matrix flawless TaC coating and a manufacturing method thereof. A tie coat is deposited on a graphite matrix. A TaC main coating is deposited on the outer layer of the tie coat. The tie coat is composed of a SiC-TaC codeposition coating or compounded by two transition layers of the SiC-TaC codeposition coating and a SiC-TaC laminated coating. When the tie coat is compounded by two transition layers of the SiC-TaC codeposition coating and the SiC-TaC laminated coating, the SiC-TaC codeposition coating serves as a first transition layer, and the SiC-TaC laminated coating serves as a second transition layer; and then the deposition of the tie coat is ended; or the SiC-TaC codeposition coating and the SiC-TaC laminated coating are alternatively deposited many times. Good TaC coating which has small heat stress, no macroscopic cracking, corrosion-resistance, and good thermal stability is deposited out of the surface of the graphite material. The method is suitable for preparing graphite substrate, graphite crucible, graphite windpipe, graphite guide shell coating in the crystal and semiconductor production, protecting and cleaning coating such as antisepsis, anti-pollution, anti-infiltration, anti-oxidation of graphite parts in other various hot environments.

The invention relates to a semiconductor production line dynamic scheduling device, comprising a sample generation module for generating data samples, a scheduling model off-line learning module for building a scheduling module according to the data sample, and a production online scheduling module used for generating a real-time scheduling strategy according to the user scheduling target and the scheduling model to perform online scheduling of the semiconductor production line. A matched scheduling model is chosen from a scheduling model database according to the user requirements; the system state information of the semiconductor production line is inputted; and the application scheduling model chooses an optimal or a close-to-optimal scheduling strategy from the candidate scheduling strategies to be applied to the operation of the production line. Compared with the prior art, the semiconductor production line dynamic scheduling device achieves the real-time performance and optimization of the scheduling, satisfies the effectiveness of the scheduling and improves the overall performance of the production line.

Individual two-dimensional barcodes 30, 91 and 173 are provided for individual chips 31 arrayed on a wafer 50, individual lead frames 93 to each of which chips 92 are bonded and individual packaged products 171 constituted of resin sealed semiconductor chips based upon chip ID information to enable information management to be implemented separately for individual chips 31, individual frames 93 and individual chip products 171. Thus, a higher degree of efficiency and a higher degree of accuracy in the information management for semiconductor devices are achieved in all processes of semiconductor production including the individual manufacturing processes, the physical distribution process, the shipping process and the claim handling process.