Semiconductor production line model building, optimizing and scheduling method based on petri net and immune arithmetic

An immune algorithm and optimal scheduling technology, applied in genetic models, calculations, control/regulation systems, etc., can solve problems such as non-timed processing, different setting times, impractical production lines, etc., to improve reusability and reduce complexity. Effect

Inactive Publication Date: 2009-07-29
TONGJI UNIV
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Problems solved by technology

Use the queuing theory to calculate the waiting time of workpieces. However, due to the different types of workpieces and processing steps, the processing time of workpieces and the setting time of equipment are also differe

Method used

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  • Semiconductor production line model building, optimizing and scheduling method based on petri net and immune arithmetic
  • Semiconductor production line model building, optimizing and scheduling method based on petri net and immune arithmetic
  • Semiconductor production line model building, optimizing and scheduling method based on petri net and immune arithmetic

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Embodiment approach

[0061] Such as image 3 As shown, according to the actual situation of the semiconductor production line, the workpiece directly enters the path selection area after passing through the "feeding area". After matching, after finding the corresponding equipment group, the workpiece is moved into the buffer of the next equipment group. After the workpiece completes a process, it is judged whether the processing is completed. If it is not completed, it will enter the path selection area again. If the processing is completed, it will enter the completion area. After the workpiece enters the completion area, the processing will stop, and there is no need to choose to go to other equipment groups. . Workpieces that fail to be processed enter the processing failure area and wait for reprocessing.

[0062] Such as Figure 4 As shown, the modeling of the equipment group takes the equipment group W1 as an example. W1 has two equipment Ma and Mb. After the workpiece enters the buffer z...

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Abstract

The invention provides an optimized scheduling method of a semiconductor production line based on a Petri net and immune algorithm. The method utilizes the Petri net for carrying out modeling to the semiconductor production line, comprising a path scheduling model, an equipment group scheduling model and an equipment scheduling model; and the immune algorithm is embedded in the Petri net model as the scheduling strategy. By the Petri net model, all possible acts of the semiconductor manufacturing system can be described, such as work-piece processing, equipment failure, batch processing, defected wafer rework and the like. The chromosome of the immune algorithm can be directly structured out of search nodes of the Petri net model, and each gene of each chromosome records the scheduling strategy of each equipment group. A better chromosome is obtained by the simulation of the Petri net model, and therefore a sub-optimal scheduling strategy is generated. The optimized scheduling method has the advantages of reducing the complexity of the model and improving the reusability of the model and the scheduling algorithm.

Description

technical field [0001] The invention relates to a semiconductor production line modeling and optimization method based on Petri nets and immune algorithms, in particular to an advanced production management method that intelligently simulates life science immune principles and genetics in production management in the field of microelectronics manufacturing. Specifically, the modeling and scheduling method involved in the present invention uses Petri nets as a modeling tool, uses immune algorithms as a scheduling method, and comprehensively considers multiple indicators such as total movement, total output, on-time delivery rate, and average production cycle. The optimization of the daily work order is determined through simulation, and the actual operation of the production line is guided accordingly. Background technique [0002] Semiconductor devices are very expensive to manufacture. Semiconductor device manufacturing is risky due to the large investment costs required. ...

Claims

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Application Information

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IPC IPC(8): G06F17/50G06N3/12G05B19/418G05B13/04
CPCY02P90/02
Inventor 吴启迪乔非曹政才李莉余红霞
Owner TONGJI UNIV
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