Cull before vertex attribute fetch and vertex lighting

a technology of vertex attributes and lighting, applied in the field of graphics processing, can solve the problems of reducing the computational load of the parallel processing subsystem, and achieve the effect of reducing the computational load of the parallel processing and saving memory bandwidth

Active Publication Date: 2013-09-24
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0013]One advantage of the disclosed method is that batches of vertices associated with primitives being processed within the graphics rendering pipeline that eventually would be culled by the VPC unit are discarded at an earlier stage in the pipeline. Such an approach saves memory bandwidth since vertex attributes associated with the disc

Problems solved by technology

In addition, early vertex culling reduces computational load on the parallel processing subsystem since the discarded vertices, and, consequen

Method used

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  • Cull before vertex attribute fetch and vertex lighting
  • Cull before vertex attribute fetch and vertex lighting
  • Cull before vertex attribute fetch and vertex lighting

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Embodiment Construction

[0025]In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

[0026]The approach to early vertex culling described herein allows vertices of one or more primitives being processed within the graphics rendering pipeline (e.g., graphics rendering pipeline 100) that eventually would be culled by the VPC unit 116 to be identified and discarded at an earlier stage in the pipeline. As described in greater detail below, when processing a batch of vertices associated with one or more primitives, each vertex is processed by a different thread of a thread group, and a clip status is generated for each vertex by the thread processing that vertex. In one embo...

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Abstract

One embodiment of the invention sets forth a mechanism for compiling a vertex shader program into two portions, a culling portion and a shading portion. The culling portion of the compiled vertex shader program specifies vertex attributes and instructions of the vertex shader program needed to determine whether early vertex culling operations should be performed on a batch of vertices associated with one or more primitives of a graphics scene. The shading portion of the compiled vertex shader program specifies the remaining vertex attributes and instructions of the vertex shader program for performing vertex lighting and performing other operations on the vertices in the batch of vertices. When the compiled vertex shader program is executed by graphics processing hardware, the shading portion of the compiled vertex shader is executed only when early vertex culling operations are not performed on the batch of vertices.

Description

BACKGROUND OF THE INVENTION[0001]1. Field of the Invention[0002]The present invention relates generally to the field of graphics processing and, more specifically, to culling before vertex attribute fetch and vertex lighting.[0003]2. Description of the Related Art[0004]A graphics processing pipeline of a graphics processing unit (GPU) accepts a representation of a three-dimensional (3D) scene as an input and processes that input to produce a 2D display image of the scene as an output. As is well known, the 3D graphics scene is typically represented by a collection of primitives having vertices. Indices associated with the vertices are stored in index arrays, and vertex data associated with those vertices is stored in vertex arrays. The primitives are individually processed by the GPU based on the index arrays and the vertex data when generating the 2D display image of the scene.[0005]FIG. 1 is a conceptual diagram different stages in a graphics processing pipeline 100 of a GPU throu...

Claims

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Application Information

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IPC IPC(8): G09G5/00
CPCG06T15/005G06T15/40G09G2360/08G09G5/393G09G2360/06G09G5/363
Inventor HAKURA, ZIYAD S.LINDHOLM, JOHN ERIKKILGARIFF, EMMETT M.OHANNESSIAN, ROBERTWHITMAN, SCOTT R.BOWMAN, JAMES C.BROWN, PATRICK R.CUNNIFF, ROSS A.
Owner NVIDIA CORP
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