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34 results about "Port performance" patented technology

Compact terahertz power synthesis frequency multiplier circuit

The invention discloses a compact terahertz power synthesis frequency multiplier circuit which comprises an upper metal substrate and a lower metal substrate, wherein a cavity formed by the upper and lower metal substrates is internally provided with an input waveguide structure, a synthesizing channel, an output waveguide structure and a direct current biasing circuit which are in the same structure, respectively, wherein one end of the synthesizing channel is connected with the input waveguide structure while the other end of the synthesizing channel is connected to the output waveguide structure; the synthesizing channel is internally provided with two thin film chips symmetrical in mirror; and one group of the thin film chips is connected to the upper metal substrate while the other group of the thin film chips is connected to the lower metal substrate. The direct current biasing circuit is provided with chip capacitors connected with the thin film chips. Based on a micro/nano technology, the compact terahertz power synthesis frequency multiplier circuit has the characteristics of compact structure and high integrating degree. The compact terahertz power synthesis frequency multiplier circuit has the characteristics of good port performance and higher power. The compact terahertz power synthesis frequency multiplier circuit has the characteristics of low cost and good consistency and is convenient for large-scale production.
Owner:SOUTHEAST UNIV

Method for testing performance of network port of set-top box

The invention discloses a method for testing the performance of a network port of a set-top box. The method comprises the following steps: (1) preparing a special network RJ45 registered jack; (2) inserting the special network RJ45 registered jack in the network port of the to-be-tested set-top box; (3) running a set-top box network port performance detection thread by the to-be-tested set-top box; (4) transmitting a network data packet back to the network port of the set-top box after passing through the registered jack, and receiving and processing the network data packet through a receiving module of the thread; (5) if the particular network data packet is not successfully received, adding 1 to a packet loss counter; (6) if the particular network data packet is received, but the data CRC in the data packet fails the verification, adding 1 to a wrong packet counter; and (7) if the particular network data packet is received, and the data CRC in the data packet passes the verification, adding 1 to a successfully received data packet counter. By adoption of the method disclosed by the invention, the link and connection correctness of the physical network port of the set-top box can be tested, the packet loss rate and the throughput of the network port of the set-top box can also be tested, and long-time pressure burn test is facilitated.
Owner:UNIONMANTECH

Port performance statistics system

The invention discloses a port performance statistics system. The system comprises a user layer, a platform interface layer and a performance statistics module, wherein the platform interface layer is separately connected with the user layer and the performance statistics module; the platform interface layer is used for obtaining a first time value that each IO arrives at a destination port and enters a queue, determining the current number of the IOs in the queue when the IOs are allocated to a thread, determining a second time value that each IO leaves the destination port after being processed at the storage end, determining each delay, and sending each delay and the current number of the IOs to the performance statistics module; and the performance statistics module is used for calculating the port performance of the destination port, wherein the port performance includes the average delay of the destination port and the real-time number of the IOs in the queue. By adopting the port performance statistics system disclosed by the embodiment of the invention, the port performance of the destination port is calculated in the platform interface layer and the performance statistics module, and thus the load pressure of a driver layer can be reduced; and the system is simple in statistical process and more accurate in statistical result.
Owner:INSPUR SUZHOU INTELLIGENT TECH CO LTD

X86 platform network port performance test method and device based on DPDK technology

The invention discloses an X86 platform network port performance test method and device based on a DPDK technology, and the method comprises the steps: obtaining a port name and a PCI bus number of a tested network port, and generating a corresponding relation table of the PCI bus number and the port name; performing PCI binding by using a DPDK script, and performing UP processing on two ports for receiving and transmitting data; performing data receiving and transmitting on two ports for receiving and transmitting data through a data receiving and transmitting tool, counting data actually received and transmitted by the two ports in each receiving and transmitting process, updating the total amount of the data, and writing the data into a log file in real time; analyzing whether the packet loss quantity and the packet loss rate are in a preset standard in a preset time period, and if the packet loss quantity and the packet loss rate exceed the preset standard, judging that the test fails and the network port performance is unqualified; and if yes, determining that the test is successful and the network port performance is qualified. According to the method, the flow, the success rate and the packet loss rate of the two ports in a period of time can be automatically counted, the test efficiency of the network port function is greatly improved, and a sufficient basis is provided for the network port performance.
Owner:BEIJING GEMOTECH INTELLIGENT TECH

Compact terahertz power synthesis frequency multiplier circuit

The invention discloses a compact terahertz power synthesis frequency multiplier circuit which comprises an upper metal substrate and a lower metal substrate, wherein a cavity formed by the upper and lower metal substrates is internally provided with an input waveguide structure, a synthesizing channel, an output waveguide structure and a direct current biasing circuit which are in the same structure, respectively, wherein one end of the synthesizing channel is connected with the input waveguide structure while the other end of the synthesizing channel is connected to the output waveguide structure; the synthesizing channel is internally provided with two thin film chips symmetrical in mirror; and one group of the thin film chips is connected to the upper metal substrate while the other group of the thin film chips is connected to the lower metal substrate. The direct current biasing circuit is provided with chip capacitors connected with the thin film chips. Based on a micro / nano technology, the compact terahertz power synthesis frequency multiplier circuit has the characteristics of compact structure and high integrating degree. The compact terahertz power synthesis frequency multiplier circuit has the characteristics of good port performance and higher power. The compact terahertz power synthesis frequency multiplier circuit has the characteristics of low cost and good consistency and is convenient for large-scale production.
Owner:SOUTHEAST UNIV
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