System and method for realizing multipath burst data business caching based on FPGA (Field Programmable Gate Array)

Abstract

The invention discloses a system and method for realizing multipath burst data business caching based on an FPGA (Field Programmable Gate Array), wherein the system comprises an off-chip cache and an FPGA chip, wherein the off-chip cache is used for caching multipath burst data, and the FPGA chip is used for providing an RAM (Random Access Memory) resource; the FPGA chip also comprises an off-chip cache controller, a multipath burst data caching management circuit, packet receiving and buffering circuits with the same number as that of data channels, a packet write control circuit, a packet read control circuit and a packet buffering and transmitting circuit, wherein the multipath burst data caching management circuit is used for processing request arbitration and channel authorization ofthe multipath burst data, generating line address information of current read / write operation and writing a packet into the off-chip cache or reading the packet from the off-chip cache. By adopting the invention, the number of the channels can be simply increased or reduced, and each path of burst data business can be relatively and evenly cached so that bottleneck caused by internal RAM shortageof an FPGA chip can be avoided.

Description

technical field [0001] The invention relates to the field of communication technology, in particular to a system and method for realizing multi-channel burst data service buffering based on FPGA. Background technique [0002] In the field of communication technology, it is often necessary to buffer and process multiple communication data services with characteristics such as burst, variable length, and non-scheduled, so that the subsequent modules can process at a fixed rate; especially for protocol conversions at different rates, it is even more necessary to The multi-channel burst data service is cached; in the existing technology, there are multiple cache methods for buffering the multi-channel burst data service, and the implementation methods are as follows. [0003] (1) It is implemented by stacking dedicated ASIC chips; however, the number of channels provided by dedicated ASIC chips is limited, and each ASIC chip needs an independent external memory chip; when r...

AI Technical Summary

Problems solved by technology

[0003] (1) It is implemented by stacking dedicated ASIC chips; however, the number of channels provided by dedicated ASIC chips is limited, and each ASIC chip needs an independent external memory chip; when realizing more channels (N>2) burst data services More ASIC chips and memory chips are needed, resulting in high hardware costs and difficult board wiring.

[0004] (2) It is realized by using FPGA on-chip RAM; the current FPGA generally provides a certain number of RAMs with fixed capacity. Using the combination of these RAM resources, each channel independently uses data queues to realize multi-channel data services. cache (see figure 1 ); but the on-chip RAM resources provided by the FPGA are very limited. On the one hand, the data queue depth allocated to multi-channel data is limited, and it cannot cope with burst data like video data; on the other hand, if a certain depth of the data queue is to be satisfied, The number of channels for caching multi-channel data becomes limited, and it is impossible to achieve more channels

[0005] (3) It is realized by using FPGA on-chip RAM and off-chip RAM chip; figure 2 In the way adopted, the multi-channel burst data service is cached in the off-chip RAM chip by the arbiter implemented by the internal logic of the FPGA in a fixed priority manner, and the length information of each data packet of each burst data is stored in the FPGA chip In the packet length RAM composed of RAM; this method is more flexible than methods (1) and (2), but there are still defects: 1. The depth of the packet length RAM implemented by the FPGA on-chip RAM determines the depth of the cache to the chip. The number of data packets of the external RAM chip, due to the limited RAM resources in the FPGA, on the one hand, the depth of the data packet length RAM is limited, that is, the number of data packets cached in the external RAM chip is limited; on the other hand, the data packet length is satisfied When the RAM depth is required, the number of channels is limited; second, when multi-channel burst data is buffered to the off-chip RAM in a fixed-priority manner, channels with high priority will cause priority The data service of the low channel cannot be processed in time, and the phenomenon of "hunger and fullness" is prone to occur

Images