Flash memory devices using large electron affinity material for charge trapping

Abstract

Disclosed is a novel flash memory device using a high-permittivity dielectric such as HfO2 or TiO2 as a charge trapping layer. Numerical simulation shows that the novel trapping material will enhance the retention time / programming speed ratio by 5 orders of magnitude, compared to the conventional Si3N4 trapping layer. Capacitors with HfO2 deposited by RTCVD as the charge trap / storage layer in SONOS-type flash memory devices were fabricated and characterized. Compared against devices with Si3N4 trapping layer, faster programming speed as well as good retention time is achieved with low programming voltage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application claims priority under 35 USC 120 from Provisional patent application Ser. No. 60 / 537,928, filed Jan. 20, 2004 which is incorporated herein by reference for all purposes.BACKGROUND OF THE INVENTION [0002] This invention relates generally to semiconductor memory devices, and more particularly the invention relates to field effect transistors having a charge storage layer between a channel region and a control gate for programming the threshold voltage for current conduction in the channel. [0003] Memory is a key component of any electronic system such as a personal computer, cellular phone, digital camera, network router, handheld personal digital assistant, etc. Demand for increased memory capacity and lower cost drives the miniaturization of semiconductor memory cells and also dictates low-power cell designs for use in future portable electronic systems. [0004] There are mainly three kinds of semiconductor memory in the...

AI Technical Summary

Benefits of technology

[0009] In accordance with the invention, a gate-stack structure is provided for a flash memory device which includes a tunnel dielectric layer on a surface of a semiconductor body over a channel region of the device. An electron-trapping dielectric layer

Problems solved by technology

It is difficult to scale down the DRAM cell size due to need for a sizable cell capacitance, however.

The data retention capability of DRAM is limited by charge leakage through p-n junctions and sub-threshold conduction in transistors; therefore DRAM needs frequent refreshing with attendant power consumption.

This thickness makes the cell relatively slow to program, even if channel hot electron injection is used.

However, SONOS memory technology faces challenges for further improvement.

Programming speed is also limited due to the fact that electrons must tunnel through a significant portion of the nitride before becoming trapped (modified FN tunneling as shown in FIG. 3(a), especially at low programming voltages.

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