Metal-oxide-semiconductor transistor and manufacturing method thereof

Abstract

The present invention provides a method for fabricating a metal oxide semiconductor transistor. First, a semiconductor substrate is provided, including a gate structure, and the gate structure has a liner layer on two opposite sidewalls. Then, a stress capping layer is formed to cover the semiconductor substrate, the gate structure and the liner layer without spacers. Next, an activation process is performed, and then an etching process is performed on the stress capping layer, so that the stress capping layer becomes a self-aligned metal silicide blocking layer. Then, a self-aligned metal silicide process is performed to form a metal silicide layer in the area not covered with the stress capping layer.

Description

technical field [0001] The present invention relates to a method for manufacturing a metal-oxide-semiconductor (MOS) transistor, in particular to a method for manufacturing a metal-oxide-semiconductor transistor with strained silicon. The feature of the present invention is to remove the spacer of the metal oxide semiconductor transistor first, and then form a stress covering layer (capstressed layer) on the metal oxide semiconductor transistor to generate structural strain, so that the metal oxide semiconductor transistor can have a higher drive current, thereby improving the operating performance of the semiconductor transistor. Background technique [0002] As semiconductor manufacturing technology becomes more and more sophisticated, integrated circuits have undergone major changes, which has led to a rapid increase in computing performance and storage capacity of computers, and has driven the rapid development of peripheral industries. The semiconductor industry is als...

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Problems solved by technology

[0008] In the prior art, the concentration of P-type dopants in the channel region 301 is reduced to increase the electron mobility of the channel region 301, but this method is limited by offsetting the spacer 311, the spacer 412, the spacer 413, and the spacer 414. The structure of the mixed covering layer 516 can only change the dopant concentration at the junction of the channel region 301 and the polysilicon gate 306, so the improvement effect of the prior art is quite limited

[0009] On the other hand, although the prior art can improve the electron mobility of the channel region 301 of the N-type metal oxide semiconductor transistor, however, since the prior art utilizes the mixed covering layer 516 to make the P-type dopant of the substrate 309 Therefore, the mixed covering layer 516 will also reduce the P-type dopant concentration of the P-type lightly doped drain (p-type lightly-doped-drain, PLDD) of the P-type metal oxide semiconductor transistor, thereby destroying the fabricated The operation of PMOS transistors

In view of this, the hybrid cover layer 516 of the prior art is completely unsuitable for PMOS transistors

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