MOS transistor with stacked nanometer lines and manufacturing method of MOS transistor

A technology of MOS transistors and stacked nanowires, which is applied in the direction of nanotechnology, nanotechnology, semiconductor/solid-state device manufacturing, etc., can solve the problems of increasing process costs, etc., and achieve the effect of increasing the effective conductive total cross-sectional area and increasing the driving current

Inactive Publication Date: 2015-01-14
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This method is severely limited by the quality of the epitaxial thin layer, which greatly increases the process cost

Method used

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  • MOS transistor with stacked nanometer lines and manufacturing method of MOS transistor
  • MOS transistor with stacked nanometer lines and manufacturing method of MOS transistor
  • MOS transistor with stacked nanometer lines and manufacturing method of MOS transistor

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Embodiment Construction

[0024] The features and technical effects of the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and in conjunction with schematic embodiments. It discloses a stacked nanowire MOS that sufficiently increases the effective width of the conductive channel and the total effective conductive cross-sectional area to increase the driving current. Transistors and methods of making them. It should be pointed out that similar reference numerals represent similar structures, and the terms "first", "second", "upper", "lower" and the like used in this application can be used to modify various device structures or manufacturing processes . These modifications do not imply spatial, sequential or hierarchical relationships of the modified device structures or fabrication processes unless specifically stated.

[0025] Figure 9 Shown is a three-dimensional schematic diagram of a stacked nanowire MOS transistor manufac...

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Abstract

The invention discloses an MOS transistor with stacked nanometer lines and a manufacturing method of the MOS transistor. The MOS transistor comprises toruliform nanometer line stacks, a plurality of grid stacks, a plurality of source and drain regions and a plurality of channel regions, wherein each nanometer line stack is formed by stacking the nanometer lines in the longitudinal direction and extends on a substrate in the first direction; the grid stacks extend in the second direction and cross over the nanometer stacks; the source and drain regions are located on the two sides of each grid stack in the second direction; the channel regions are formed by the nanometer line stacks between the source and drain regions. According to the MOS transistor with the stacked nanometer lines and the manufacturing method of the MOS transistor, the toruliform nanometer line stacks with good quality are formed by means of etching carried out many times and sideward etching and filling of grooves, effective widths of conducting channels are increased at low cost, the total area of effective conductive sections is increased and drive currents are increased.

Description

technical field [0001] The invention relates to a semiconductor device and a manufacturing method thereof, in particular to a novel beaded stacked nanowire MOS transistor and a manufacturing method thereof. Background technique [0002] In the current sub-20nm technology, the three-dimensional multi-gate device (FinFET or Tri-gate) is the main device structure, which enhances the gate control ability and suppresses leakage and short channel effects. [0003] For example, compared with traditional single-gate bulk Si or SOI MOSFETs, MOSFETs with double-gate SOI structures can suppress short-channel effects (SCE) and drain-induced barrier lowering (DIBL) effects, have lower junction capacitance, and can To achieve light channel doping, the threshold voltage can be adjusted by setting the work function of the metal gate, which can obtain about 2 times the driving current and reduce the requirements for the effective gate oxide thickness (EOT). Compared with the double-gate dev...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336H01L29/78H01L29/10B82Y10/00
CPCH01L29/7853H01L29/7854H01L29/66439H01L29/0673H01L29/78696
Inventor 殷华湘马小龙徐唯佳徐秋霞朱慧珑
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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