This invention belongs to the field of
integrated circuit design, specifically relating to a method for predicting S-parameters of
chip interconnects based on hierarchical parasitic modeling. It aims to address the problems of weak generalization ability of
machine learning methods in
chip interconnect
signal integrity analysis and the
neglect of
electromagnetic coupling effects caused by the switching of
reference plane return current between vertical interconnects and horizontal traces, resulting in insufficient accuracy and poor adaptability of S-parameter prediction. The solution includes: normalizing the
layout geometry description of the
chip high-frequency interconnect structure, decomposing and mapping it into a standardized parallel
bus substructure; constructing an initial
equivalent circuit model based on a parasitic parameter extraction model; optimizing and correcting the initial parasitic parameters using a neural network parasitic parameter adapter, wherein the
transmission line adapter corrects the parameters through high-order
nonlinear transformation and projection function, and the vertical interconnect adapter jointly models the
electromagnetic coupling effect between vertical interconnects and
transmission line segments; injecting the corrected high-fidelity parasitic parameters into the circuit model, and generating S-parameters through circuit
simulation.