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4 results about "Signal integrity analysis" patented technology

A PCB layout optimization method suitable for signal transmission

ActiveCN121683691BDesign phaseAutomatic routing
This application relates to the field of electronic circuit design technology, and in particular to a PCB layout optimization method suitable for signal transmission. This method acquires manufacturer-specific process capability parameters, constructs a manufacturing disturbance model including conductor geometric deviations, dielectric non-uniformity, and interlayer alignment errors, and embeds an electromagnetic simulation engine to form a dynamic signal integrity analysis model. Based on this, an adaptive layout constraint rule set is generated, driving the layout and routing algorithm to perform manufacturing robustness-oriented automatic routing. This solves the problem of signal integrity degradation in high-speed signal links on PCBs due to manufacturing fluctuations, pre-compensating for manufacturing-introduced non-ideals during the design phase, and improving the first-pass success rate and signal performance consistency of high-speed PCBs.
Owner:JIANGXI MATT MICROELECTRONICS CO LTD

A method for predicting S-parameters of core particle interconnection based on hierarchical parasitic modeling

PendingCN122334161AAlgorithmHemt circuits
This invention belongs to the field of integrated circuit design, specifically relating to a method for predicting S-parameters of chip interconnects based on hierarchical parasitic modeling. It aims to address the problems of weak generalization ability of machine learning methods in chip interconnect signal integrity analysis and the neglect of electromagnetic coupling effects caused by the switching of reference plane return current between vertical interconnects and horizontal traces, resulting in insufficient accuracy and poor adaptability of S-parameter prediction. The solution includes: normalizing the layout geometry description of the chip high-frequency interconnect structure, decomposing and mapping it into a standardized parallel bus substructure; constructing an initial equivalent circuit model based on a parasitic parameter extraction model; optimizing and correcting the initial parasitic parameters using a neural network parasitic parameter adapter, wherein the transmission line adapter corrects the parameters through high-order nonlinear transformation and projection function, and the vertical interconnect adapter jointly models the electromagnetic coupling effect between vertical interconnects and transmission line segments; injecting the corrected high-fidelity parasitic parameters into the circuit model, and generating S-parameters through circuit simulation.
Owner:SHENZHEN BIANGXIN TECH CO LTD

Model-driven optoelectronic integrated link analysis system and method

The application relates to a model-driven optoelectronic integrated link analysis system and method. The system comprises a signal transmitting end model for generating an original electrical signal; an electrical interconnection model comprising at least one electrical interconnection sub-model for simulating input-output characteristics of an electrical interconnection device and outputting a primary electrical signal according to the original electrical signal; an electro-optical-electrical equivalent model comprising at least one electro-optical-electrical equivalent sub-model for simulating input-output characteristics of an electro-optical-electrical link and outputting a secondary electrical signal according to the primary electrical signal; and a signal receiving end model for analyzing the secondary electrical signal to obtain an analysis result. The system solves the problems of complicated construction of an optoelectronic interconnection model and difficult signal integrity analysis in existing optoelectronic integrated link modeling.
Owner:ZHEJIANG LAB