11 results about "Signal integrity analysis" patented technology

The invention relates to the field of digital circuit design, and provides a method for optimizing noise influence of a synchronous switch in an IBIS model. When a traditional IBIS model measures pull-up / pull-down characteristics, it is assumed that a power supply and ground potential are constant, voltage fluctuation actually caused by a synchronous switch is ignored, and the simulation precision of a high-speed interface is reduced. By collecting current response data of a pull-up circuit and a pull-down circuit of the buffer under different power supply / ground fluctuations, pull-up and pull-down power supply modulation coefficients are calculated respectively, and the influence of power supply voltage disturbance on output current is represented. In the simulation stage, the output current in the IBIS model is dynamically modulated according to the power supply and ground potential change caused by the real-time SSN, so that the simulation is closer to the real chip behavior. The method does not need to modify a model structure, is compatible with an existing process, remarkably improves the accuracy of high-speed signal integrity analysis, is suitable for design verification of DDR, PCIe and other high-density parallel interfaces, and effectively supports the system-level power supply and signal co-simulation requirements.

The invention relates to the technical field of high-speed wire harness shaping, in particular to a high-speed wire harness shaping method and system based on intelligent visual identification, and the method comprises the steps: carrying out the image collection of a positioned high-speed wire harness, obtaining a plurality of wire harness two-dimensional images and a plurality of pieces of structured light information, constructing a wire harness skeleton model, obtaining a wire harness morphology parameter set, and carrying out the recognition of the two-dimensional images; inputting the wire harness morphology parameter set into a pre-constructed signal integrity analysis model to obtain a wire harness analysis result, if the wire harness analysis result is that shaping is needed, taking the high-speed wire harness as a to-be-shaped wire harness, making a shaping strategy set, shaping the to-be-shaped wire harness to obtain a shaped wire harness, and if the wire harness analysis result is that shaping is not needed, taking the high-speed wire harness as the to-be-shaped wire harness, making a shaping strategy set, shaping the to-be-shaped wire harness to obtain a shaped wire harness; if yes, the high-speed wire harness serves as a standard high-speed wire harness, the shaped wire harness or the standard high-speed wire harness serves as a qualified high-speed wire harness, and high-speed wire harness shaping based on intelligent visual recognition is completed based on the qualified high-speed wire harness. According to the invention, high-precision and high-efficiency wire harness intelligent shaping can be realized.

This application relates to the field of electronic circuit design technology, and in particular to a PCB layout optimization method suitable for signal transmission. This method acquires manufacturer-specific process capability parameters, constructs a manufacturing disturbance model including conductor geometric deviations, dielectric non-uniformity, and interlayer alignment errors, and embeds an electromagnetic simulation engine to form a dynamic signal integrity analysis model. Based on this, an adaptive layout constraint rule set is generated, driving the layout and routing algorithm to perform manufacturing robustness-oriented automatic routing. This solves the problem of signal integrity degradation in high-speed signal links on PCBs due to manufacturing fluctuations, pre-compensating for manufacturing-introduced non-ideals during the design phase, and improving the first-pass success rate and signal performance consistency of high-speed PCBs.

This invention belongs to the field of integrated circuit design, specifically relating to a method for predicting S-parameters of chip interconnects based on hierarchical parasitic modeling. It aims to address the problems of weak generalization ability of machine learning methods in chip interconnect signal integrity analysis and the neglect of electromagnetic coupling effects caused by the switching of reference plane return current between vertical interconnects and horizontal traces, resulting in insufficient accuracy and poor adaptability of S-parameter prediction. The solution includes: normalizing the layout geometry description of the chip high-frequency interconnect structure, decomposing and mapping it into a standardized parallel bus substructure; constructing an initial equivalent circuit model based on a parasitic parameter extraction model; optimizing and correcting the initial parasitic parameters using a neural network parasitic parameter adapter, wherein the transmission line adapter corrects the parameters through high-order nonlinear transformation and projection function, and the vertical interconnect adapter jointly models the electromagnetic coupling effect between vertical interconnects and transmission line segments; injecting the corrected high-fidelity parasitic parameters into the circuit model, and generating S-parameters through circuit simulation.

The invention relates to the technical field of signal simulation, in particular to a high-frequency PCB signal integrity simulation method and system and a storage medium. Comprising the following steps: constructing a multilayer dielectric model of a high-frequency circuit board, and extracting electrical characteristic data to obtain signal waveform distribution; determining a reference time sequence based on signal waveform distribution, performing Monte Carlo simulation in combination with environmental factors, generating a plurality of signal distortion scenes, analyzing waveform distortion, and identifying a high-risk propagation path; extracting high-risk path segment feature data, constructing a signal integrity evaluation matrix, and analyzing a signal distortion root; adjusting multi-layer medium parameters according to a classification result, and generating optimized path configuration; extracting a signal integrity index, verifying the effectiveness of an optimized path, generating a comprehensive report, predicting the signal distortion probability, and providing a basis for the design of a high-frequency circuit board. According to the method, the problems of signal integrity analysis and optimization of the high-frequency PCB are solved, and accurate optimization of the signal propagation path and effective prediction of the signal distortion probability are realized.

The invention relates to the technical field of electrical measurement, in particular to an FFC connector signal integrity analysis method and related device.The method comprises the steps that electromagnetic field signals at the two ends of an FFC connector in the working state are obtained according to an electromagnetic sensor, change characteristics related to signal transmission are obtained, and integrity performance of the two ends of the FFC connector in the signal transmission process is evaluated; obtaining a quality parameter set; comparing the difference vectors of the signal transmission parameters at the two ends in the parameter set, and calculating the difference range of the difference vectors and the standard transmission performance; and generating abnormal distribution data marking abnormal pins and positions according to the difference range, and performing spatial positioning and quantitative processing on the abnormal distribution data to obtain an analysis report. According to the invention, the diagnosis capability of abnormal problems is optimized through spatial positioning and quantitative processing, and efficient technical support is provided for application of the FFC connector in a high-density integrated circuit and high-speed data transmission equipment, so that the data error rate is effectively reduced, and the performance stability is improved.

The application relates to a model-driven optoelectronic integrated link analysis system and method. The system comprises a signal transmitting end model for generating an original electrical signal; an electrical interconnection model comprising at least one electrical interconnection sub-model for simulating input-output characteristics of an electrical interconnection device and outputting a primary electrical signal according to the original electrical signal; an electro-optical-electrical equivalent model comprising at least one electro-optical-electrical equivalent sub-model for simulating input-output characteristics of an electro-optical-electrical link and outputting a secondary electrical signal according to the primary electrical signal; and a signal receiving end model for analyzing the secondary electrical signal to obtain an analysis result. The system solves the problems of complicated construction of an optoelectronic interconnection model and difficult signal integrity analysis in existing optoelectronic integrated link modeling.

The invention relates to the technical field of signal analysis, and discloses a high-speed signal integrity analysis method, system and device and a medium, and the method comprises the steps: configuring a measuring instrument and a probe; amplitude-phase errors are eliminated through de-embedding calibration; acquiring original time domain or frequency domain signal data, and preprocessing to obtain a signal sequence with a high signal-to-noise ratio; constructing a channel model based on a transmission line theory, including performing noise suppression processing on the de-embedded frequency domain response and improving the time delay resolution capability of a reflection point through a super-resolution algorithm; utilizing a sparse reflection model to position impedance discontinuous points; aiming at a plurality of parallel lines, a multi-conductor transmission line model is adopted to separate crosstalk signals; carrying out jitter and phase noise modeling; the reflection time delay and the crosstalk propagation time delay estimated in the channel model are converted into physical distances, and positioning of a reflection point or a crosstalk source is achieved. According to the invention, the problem of step / pulse response distortion caused by limited bandwidth, discontinuous impedance and weak reflection of an instrument in a traditional high-speed signal integrity test is solved.

The invention relates to the technical field of electronic circuit design, in particular to a PCB layout optimization method suitable for signal transmission, and the method comprises the steps: building a manufacturing disturbance model comprising conductor geometric deviation, medium heterogeneity and interlayer alignment error through obtaining the specific process capability parameters of a manufacturer, and optimizing the layout of the PCB; and an electromagnetic simulation engine is embedded to form a dynamic signal integrity analysis model, a self-adaptive layout constraint rule set is generated based on the model, and a layout wiring algorithm is driven to execute manufacturing robustness-oriented automatic wiring. Therefore, the problem that the signal integrity of a high-speed signal link of the PCB is degraded due to manufacturing fluctuation is solved, non-ideality introduced by manufacturing is compensated in advance in the design stage, and the one-time board throwing success rate and the signal performance consistency of the high-speed PCB are improved.

The invention provides a high-speed signal integrity analysis method, device and equipment and a storage medium, and the method comprises the steps: carrying out the collection and feature extraction of an S parameter matrix, an impedance parameter and an input signal feature parameter of a transmission line, and obtaining a link system feature vector; predicting an insertion loss response waveform and a near-end crosstalk response waveform of the target transmission line in parallel according to the feature vector; carrying out superposition and filtering processing on the prediction waveform in a time domain to obtain a complete output signal waveform; and generating a signal eye pattern according to the output waveform, extracting measurement parameters, and performing signal integrity evaluation. According to the method, efficient and accurate multi-channel high-speed signal integrity analysis is realized through a parallel prediction mechanism, and the PCB design verification efficiency is remarkably improved.

The invention discloses a chip array field intensity distribution prediction method and system based on spatial information, and relates to the technical field of chip array electromagnetic field prediction. The method comprises the following steps: constructing a multi-channel input tensor, and carrying out pixel-level fusion on a spatial information pixel matrix representing geometric layout and a frequency matrix representing a working state, so that a network can learn a local physical dependency relationship; an asymmetric down-sampling codec architecture E-300Net is adopted, in down-sampling and up-sampling paths, convolution and deconvolution operations with the stride of 2 and the stride of 3 are configured in a mixed mode, so that it is ensured that feature maps input in any size can still be accurately aligned and high-fidelity space details are reserved when the feature maps input in any size are processed. According to the method, the simulation efficiency is remarkably improved, the simulation time is shortened to the second level, meanwhile, high-precision and high-generalization-ability electric field intensity prediction is achieved, and the engineering requirements of chip electromagnetic compatibility and signal integrity analysis are met.