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A method and application of chip test socket structure design based on fea simulation

A technology of chip testing and simulation design, applied in CAD circuit design, electronic circuit testing, computer-aided design, etc., can solve problems such as logic errors and propagation delays, reduce signal interference, ensure test accuracy, and save test costs Effect

Active Publication Date: 2021-03-09
SUZHOU TAOSHENG ELECTRONICS TECH CO LTD
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AI Technical Summary

Problems solved by technology

Moreover, in high-speed and high-frequency systems, crosstalk, as an objective phenomenon, will cause propagation delays and logic errors, often making the test system in trouble

Method used

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  • A method and application of chip test socket structure design based on fea simulation
  • A method and application of chip test socket structure design based on fea simulation
  • A method and application of chip test socket structure design based on fea simulation

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Embodiment Construction

[0030] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

[0031] The simulation tool of the present invention is based on Maxwell's equations:

[0032]

[0033]

[0034] ▽·D(r,t)=ρ(r,t)

[0035] ▽·B(r,t)=0

[0036] Among them, E, B, H, D, J and ρ are real variable functions of position (r) and time (t), and the corresponding names and units are as follows:

[0037] H(r,t)——magnetic field density (A / m);

[0038] E(r,t)——electric field strength (V / m);...

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Abstract

The invention relates to a method for designing a structure of a chip test socket based on FEA simulation. First, a 3D model of digital signal transmission is established in simulation software, then a simulation circuit model is built according to the 3D model, voltage distribution is counted, and sampling results are obtained according to the simulation circuit model again. , obtain the equivalent distribution of noise, according to the equivalent distribution of noise, simulate and choose to add one or more probes at the noise position to form multiple probe addition schemes, and finally make the impedance of the chip test socket circuit through the signal integrity analysis results. To achieve the best match, get the best probe adding position and probe length scheme. Compared with the traditional chip testing method and base, the invention adds some grounding probes of specific length to wrap the transmission signal, which can effectively reduce the interference of the signal, select the appropriate probe and probe position through the FEA simulation tool, and design the optimal chip Test sockets can save test costs to the greatest extent and ensure chip test accuracy.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a method for designing a chip testing socket structure based on FEA simulation and its application. Background technique [0002] With the rapid development of integrated circuits, the feature size of the process is getting smaller and smaller, and the input and output leads of the chip have increased sharply. The crosstalk problem caused by the coupling capacitance and coupling inductance between adjacent lines has become quite serious. Crosstalk may be the most important factor affecting high-speed data transmission. Crosstalk is an undesired amount of energy produced by the coupling of one signal to another. According to Maxwell's law, as long as there is a current, there will be a magnetic field, and the interference between the magnetic fields is the source of crosstalk. This induced signal may cause loss of data transmission and transmission errors. Therefor...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/398G01R31/28G01R31/26
CPCG01R31/2884G06F30/39
Inventor 施元军郭靖刘凯
Owner SUZHOU TAOSHENG ELECTRONICS TECH CO LTD
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