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FEA simulation-based chip test socket structure design method and application thereof

A technology of chip testing and simulation design, applied in CAD circuit design, electronic circuit testing, special data processing applications, etc., can solve problems such as propagation delay and logic errors, reduce signal interference, ensure test accuracy, and save test cost effect

Active Publication Date: 2018-02-23
SUZHOU TAOSHENG ELECTRONICS TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Moreover, in high-speed and high-frequency systems, crosstalk, as an objective phenomenon, will cause propagation delays and logic errors, often making the test system in trouble

Method used

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  • FEA simulation-based chip test socket structure design method and application thereof
  • FEA simulation-based chip test socket structure design method and application thereof
  • FEA simulation-based chip test socket structure design method and application thereof

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Embodiment Construction

[0030] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts fall within the protection scope of the present invention.

[0031] The simulation tool of the present invention is based on Maxwell's equations:

[0032]

[0033]

[0034] ▽·D(r,t)=ρ(r,t)

[0035] ▽·B(r,t)=0

[0036] Among them, E, B, H, D, J and ρ are real variable functions of position (r) and time (t), and the corresponding names and units are as follows:

[0037] H(r,t)——magnetic field density (A / m);

[0038] E(r,t)——electric field strength (V / m);...

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Abstract

The invention relates to an FEA simulation-based chip test socket structure design method. The method comprises the steps of firstly in simulation software, building a 3D model of digital signal transmission; secondly according to the 3D model, building a simulation circuit model, and performing statistics on a voltage distribution condition; thirdly according to the simulation circuit model, obtaining a sampling result, and obtaining a noise equivalent distribution condition; fourthly according to the noise equivalent distribution condition, adding one or more probes to a noise position through simulative selection to form multiple probe addition schemes; and finally enabling impedance of a chip test socket circuit to reach the best match through a signal integrity analysis result, and obtaining optimal probe addition position and probe length schemes. Compared with conventional chip test method and base, a few grounded probes with the specific lengths are added for wrapping a transmitted signal, so that signal interference can be effectively reduced; and the proper probes and the probe positions are selected through an FEA simulation tool, and an optimal chip test socket is designed, so that the test cost is reduced to the maximum extent and the chip test precision is ensured.

Description

technical field [0001] The invention relates to the technical field of semiconductor testing, in particular to a method for designing a chip testing socket structure based on FEA simulation and its application. Background technique [0002] With the rapid development of integrated circuits, the feature size of the process is getting smaller and smaller, and the input and output leads of the chip have increased sharply. The crosstalk problem caused by the coupling capacitance and coupling inductance between adjacent lines has become quite serious. Crosstalk may be the most important factor affecting high-speed data transmission. Crosstalk is an undesired amount of energy produced by the coupling of one signal to another. According to Maxwell's law, as long as there is a current, there will be a magnetic field, and the interference between the magnetic fields is the source of crosstalk. This induced signal may cause loss of data transmission and transmission errors. Therefor...

Claims

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Application Information

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IPC IPC(8): G06F17/50G01R31/28
CPCG01R31/2884G06F30/39
Inventor 施元军郭靖刘凯
Owner SUZHOU TAOSHENG ELECTRONICS TECH CO LTD
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