Time interpolation flash adc having automatic feedback calibration

Abstract

An input signal is compared to 2N - 1 reference voltages to generate 2N - 1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

Description

[0001] This application is a continuation-in-part of US Patent Application No. 12 / 002,153 filed on December 13, 2007. technical field [0002] Embodiments relate generally to analog-to-digital conversion circuits, and more particularly to flash-type analog-to-digital conversion circuits. Background technique [0003] In basic form, an N-bit flash-type analog-to-digital (A / D) converter (hereinafter referred to as "ADC") has (2 N -1) comparators, arranged in cardinal order for comparing the same input signal with (2 N -1) Each major sequence of equally spaced reference voltages is compared. The voltage separation between each comparator and its adjacent high and / or low comparators is typically one least significant bit (LSB) of the N-bit output. [0004] In operation, all (2 N - 1) Comparators all receive the same sampling clock (typically periodic at the sampling rate) and generate a broadside output (broadside output) every clock pulse, for all comparators whose signal ex...

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Problems solved by technology

Distortion and noise introduced by the extended "hold" time of the internal sample-and-hold circuit is another concern

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