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Binary translation stack operation accelerated processing method and processor thereof

A stack operation and processing method technology, which is applied in the field of binary translation stack operation acceleration processing method and its processor, can solve problems affecting binary translation system performance and code density, and achieve the effect of enhancing flexibility, scope of use, and improving performance

Active Publication Date: 2015-03-25
C SKY MICROSYST CO LTD
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to overcome the problem that the existing binary translation system requires multiple processor instructions to affect the performance and code density of the binary translation system when processing stack operations, the present invention provides a binary translation stack operation acceleration processing method and its processor, and proposes A binary translation stack operation acceleration instruction pair, only one instruction is needed to complete the reading or writing of binary translation stack data, the adjustment of the stack pointer, the check of the stack boundary and the out-of-bounds processing, while ensuring that the processor hardware resources remain unchanged effectively improve the performance and code density of the binary translation system

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  • Binary translation stack operation accelerated processing method and processor thereof
  • Binary translation stack operation accelerated processing method and processor thereof
  • Binary translation stack operation accelerated processing method and processor thereof

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Embodiment 1

[0037] refer to Figure 1 to Figure 5 , a binary translation stack operation acceleration processing method, the acceleration processing method includes a stack data loading instruction and a stack data storage instruction;

[0038] The processing procedure of the stack data loading instruction is as follows: complete the detection of the binary translation stack boundary according to the stack boundary general register and the stack pointer general register, and obtain the stack access address according to the calculation of the stack pointer general register when it is detected that the stack access is not out of bounds, and then set The data at the address pointing to the stack is sequentially loaded into the target general-purpose register set, and the stack pointer general-purpose register is adjusted according to the loaded data width; when a stack access violation is detected, the program counter of the stack data loading instruction is added to the instruction width Th...

Embodiment 2

[0055] refer to Figure 4 and Figure 5 , a binary translation stack operation acceleration processor, including a binary translation stack operation acceleration instruction pair decoding unit, a binary translation stack operation control unit, a binary translation stack operation data processing unit and a general-purpose register file:

[0056] Binary translation stack operation acceleration instruction pair decoding unit, according to the instruction code to know whether the currently processed instruction is a stack data load instruction or a stack data storage instruction, and obtain the metadata width and stack upper boundary general registers, stack lower boundary general registers, stack Pointer general registers, stack out-of-bounds transfer address general registers, target general register sets, and source general register sets correspond to register numbers;

[0057] The binary translation stack operation control unit is connected to the output terminal of the bi...

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Abstract

A binary translation stack operation accelerated processing method includes a stack data loading instruction and a stack data storage instruction, the two instructions finish reading, writing, modification of a stack pointer, inspection of stack boarder crossing and processing of stack boarder crossing on the basis of a stack boarder universal register, a stack pointer universal register, a stack boarder crossing transfer address universal register, a source universal register set and a target universal register set, and finish updating of the state of a processor according to whether stack access crosses the boarder or not. The invention provides the binary translation stack operation accelerated processor. On the situation that it is guaranteed that hardware resources are unchanged, binary translation system performance and code density are greatly improved.

Description

technical field [0001] The invention relates to the field of Java virtual machines, in particular to a binary translation stack operation acceleration processing method and a processor thereof. Background technique [0002] The binary translation system (such as the Java virtual machine) generally transfers program variables through the stack. Each variable transfer includes two processes of writing the stack and reading the stack. Writing the stack is used to store the variable data to be transferred into the stack address pointed to by the stack pointer and Adjust the stack pointer, and read the stack to get the required data from the stack and adjust the stack pointer. Based on the security considerations of the system, before writing and reading the stack each time, it is necessary to detect and process the stack crossing behavior according to the amount of data passed and the current stack pointer. These stack operations often require multiple processor instructions to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/455
Inventor 刘智力卢星星张文蒙
Owner C SKY MICROSYST CO LTD
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