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Instruction processing method and processor

An instruction processing and processor technology, applied in the field of instruction processing methods and processors, can solve the problems of instruction mode switching, instruction decoding and execution complexity, and achieve the effect of reducing the scope of coding space

Pending Publication Date: 2021-01-26
童先娥
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This brings problems such as instruction mode switching, instruction decoding and execution complexity.

Method used

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  • Instruction processing method and processor
  • Instruction processing method and processor

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Embodiment Construction

[0039]The principles and features of the present invention are described below in conjunction with the examples, which are only used to explain the present invention, and are not intended to limit the scope of the present invention.

[0040] An embodiment of the present invention provides a processor, which includes 16 general-purpose registers, and the 16 general-purpose registers are divided into two groups, wherein one group is defined as address registers, and the other group is defined as integer registers; the address The registers are used to store memory addresses, and the integer registers are used to store integer data.

[0041] When parsing specific instructions, the processor combines two sets of general-purpose registers and adopts a special instruction processing method to reduce the number of bits used by the instruction set without affecting the flexibility and efficiency of the instruction set. The 16bits compressed instruction set can accommodate more functio...

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Abstract

The invention relates to an instruction processing method and a processor, and the method comprises the steps of dividing 16 universal registers equally into two groups, defining one group as an address register, and defining the other group as an integer register, wherein the address register is used for storing a memory address, and the integer register is used for storing integer data; when a specific instruction is parsed, respectively using 3bit operands for pointing to the address register or the integer register which is used as a source register or a target register. According to the present invention, on the basis of hardly influencing the flexibility and high efficiency of an instruction set, the bit number used by the instruction set can be reduced, so that the 16bits compressedinstruction set can accommodate more functions, the effect of using less 32-bit instructions or not using 32-bit instructions in a mixed manner is achieved, and the code density and the execution efficiency are further improved.

Description

technical field [0001] The invention relates to a computer instruction set, in particular to an instruction processing method and a processor. Background technique [0002] The instruction set is the lowest-level machine instruction that controls the work of computer hardware, and it is also a binary instruction that the CPU can directly recognize. An instruction set defines a computer hardware design and architecture. With the development of computer systems, it is required that the structure of the computer instruction system can make the overall performance of the computer faster and more efficient. The basic requirements for a well-designed instruction set are: integrity, regularity and high efficiency. [0003] Currently, well-known instruction sets are divided into two categories: complex instruction set (Complex Instruction Set Computing, referred to as CISC) and reduced instruction set (Reduced Instruction Set Computing, referred to as RISC). The characteristic of ...

Claims

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Application Information

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IPC IPC(8): G06F9/30
CPCG06F9/3012Y02D10/00
Inventor 童先娥
Owner 童先娥
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