Single event upset characteristic testing method for partially triple modular redundancy reinforced SRAM (static random access memory) type FPGA (field programmable gate array)

Abstract

The invention provides a single event upset characteristic testing method for partially triple modular redundancy reinforced SRAM (static random access memory) type FPGA (field programmable gate array). The method comprises the following steps: irradiating a tested device at a set fluence rate, recording a single event error for once when the output characteristic of the device is not correct and the functions of the device do not return to normal within time T1 after the particle irradiation stops, and repeating the above steps for multiple times and then calculating a single even error section; reducing the particle fluence rate continuously till the single even error section becomes stable; and repeating the above steps under at least five different LET values in total.

Description

technical field [0001] The invention belongs to the field of particle irradiation testing, and in particular relates to a method for testing the single-particle flipping characteristics of a SRAM-type FPGA partially reinforced by triple-mode redundancy. Background technique [0002] SRAM-type FPGA is composed of configuration memory, block memory, flip-flop, global control register and semi-blocking structure, etc., with its high integration, strong flexibility, and short development cycle, it has been more and more widely used in the aerospace field . However, there are a large number of high-energy particles such as gamma photons, radiation band electrons, and high-energy protons in the space environment where it works, and the SRAM-type FPGA is a single-event flip-sensitive device, which consists of configuration memory, block memory, flip-flops, global control registers and Compositions such as semi-blocking structures, each part may produce single-event flips under the...

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Problems solved by technology

However, triple-mode redundancy will increase the internal resource usage of the device. In some applications, due to the large amount of resources used, and the total amount of internal resources of the device is certain, it is impossible to design all circuits with triple-mode redundancy. Influence degree, three-mode redundancy is implemented for some key circuits with large impact, and triple-mode redundancy is not adopted for the rest

This kind of single-event turnover characteristic test of devices after partial triple-mode redundancy is currently a difficult point in the world, and it is impossible to accurately test the single-event turnover characteristics of part of the SRAM FPGA after triple-mode redundancy reinforcement.

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