The invention provides a particle fluence rate selection method for a large scale integrated circuit accelerator single particle test. The particle fluence rate selection method for the large scale integrated circuit accelerator single particle test including the following steps: S1, judging whether the DICE design is adopted inside a large scale integrated circuit or not, S2, conducting high-fluence rate irradiation on the large scale integrated circuit according to the ASTMF 1192 standard code if the DICE design is adopted, S3, judging whether the TMR is adopted in the large scale integrated circuit or not according to the procedures used by the large scale integrated circuit if the DICE design is not adopted, S4, conducting low-fluence rate irradiation on the large scale integrated circuit if the TMR is adopted, S5, judging whether the EDAC is adopted in the large scale integrated circuit or not according to the procedures used by the large scale integrated circuit if the TMF is not adopted, S6, conducting the low-fluence rate irradiation on the large scale integrated circuit if the EDAC is adopted, and S7, conducting the high-fluence rate irradiation on the large scale integrated circuit if the EDAC is not adopted. Compared with the prior art that only the high-fluence rate irradiation is used, the particle fluence rate selection method for the large scale integrated circuit accelerator single particle test improves irradiation evaluation accuracy.