Quantitative analysis method for heavy-ion single-particle multi-bit upset effect of device

Abstract

The present invention discloses a quantitative analysis method for a heavy-ion single-particle multi-bit upset effect of a device. The method comprises: selecting a type of heavy ions, setting an appropriate fluence rate according to a corresponding principle to perform radiation on a cover opening device, recording logic addresses and data of storage units, which perform single-particle upset, of the device by a test system, and stopping radiation when reaching an estimated single-particle upset number or the maximum ion fluence; establishing a mapping relationship from the logic addresses of the device to physical addresses, and according to a physical bit map, carrying out statistics on a number of single-particle upsets, a number of single-particle unit upset events and a number of multi-bit upset events; and by combining ion fluence, calculating parameters such as probabilities of the single-particle unit upset events and the multi-bit upset events, a multi-bit upset mean, a multi-bit upset cross section and the like. According to the quantitative analysis method for the heavy-ion single-particle multi-bit upset effect of the device, technical support and information can be provided for an anti-single-particle-upset reinforcement design of the device, and effectiveness of a reinforcement technology is verified and evaluated.

Description

technical field [0001] The invention relates to a quantitative analysis method for the heavy ion single particle multi-position flip effect of a device, and belongs to the research field of space single particle effect ground simulation test technology and reinforcement technology. Background technique [0002] With the continuous improvement of the performance requirements of large-scale integrated circuits in satellite electronic systems, the use of ultra-deep submicron and nanoscale integrated circuits has become an inevitable development trend. The primary problem brought about by the reduction of the device feature process size is the reduction of the critical charge. The critical charge is the minimum charge required for the device to undergo a single-event flip. It is inversely proportional to the square of the process size. In this case, the critical charge of the device is already less than 2fC. This means that after high-energy particles enter the device, the ioni...

AI Technical Summary

Problems solved by technology

Usually, when carrying out the device single event effect test, the test system measures and obtains the single event flip test data based on the logical address, so it cannot objectively reflect whether the memory cells where the single event flip occurs are physically adjacent and whether they can be judged as real single event multiple bit flip

On the other hand, even if the physical bitmap of the device is obtained, and the mapping from the logical address to the physical address of the single event flip is established, the selection of the ion fluence rate is not controlled in the effect test, and the conventional single event effect test method is selected. Flux rate range 10 2 -10 5 / cm 2 Any fluence rate between .s is easy to introduce "false" multi-bit flips caused by different particles incident at adjacent physical positions, resulting in excessive statistical errors of single-particle multi-bit flips

At the same time, there is a lack of clear understanding of the characterization of single-event multi-bit flipping, resulting in the definition and calculation of multi-bit flipping not being able to accurately and effectively reflect the sensitivity of devices to single-event multi-bit flipping

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