Method for testing single event upset characteristics of partial triple modular redundancy static random access memory (SRAM) type field programmable gate arrays (FPGA)

Abstract

The invention provides a method for testing single event upset characteristics of partialparts of triple modular redundancy static random access memory (SRAM) type field programmable gate arrays (FPGA). The method comprises the steps of irradiating a device to be tested under the preset fluence rate, recording one single-particle error when the output characteristic of the device is incorrect and functions of the device do not get right in time T1 for stopping particle beam irradiation, and calculating a single-particle error section after multiple repetition; continuously reducing the particle fluence rate until the single-particle error section tends to be stable; and providing another comparison device which is not subjected to triple modular redundancy fixing, irradiating the comparison device under the comparison fluence rate, calculating a single-particle error section, and then calculating the ratio of the single-particle error section of the comparison device to the single-particle error section of the device to be tested.

Description

Technical field [0001] The invention belongs to the field of particle irradiation testing, and in particular relates to a method for testing the single event inversion characteristics of an SRAM FPGA after partial three-mode redundancy reinforcement. Background technique [0002] SRAM FPGA is composed of configuration memory, block memory, flip-flops, global control registers and semi-latching structure. With its high integration, strong flexibility and short development cycle, it has been widely used in the aerospace field. . However, there are a large number of high-energy particles such as gamma photons, radiated electrons, and high-energy protons in the working space environment. SRAM FPGA is a single-event flip sensitive device, which consists of configuration memory, block memory, flip-flops, global control registers and With a semi-latched structure and other components, each part may produce a single event flip under the bombardment of high-energy particles, which has a ...

AI Technical Summary

Problems solved by technology

However, triple-mode redundancy will increase the internal resource usage of the device. In some applications, due to the large amount of resources used, and the total amount of internal resources of the device is certain, it is impossible to design all circuits with triple-mode redundancy. Influence degree, three-mode redundancy is implemented for some key circuits with large impact, and triple-mode redundancy is not adopted for the rest

Because only partial redundancy, not all circuits are redundant, it is impossible to predict whether the anti-single event upset performance of the device can be really improved after partial redundancy. The single event upset of the device after partial triple-mode redundancy Characteristic testing is currently a difficult point in the world. At present, there is no method to test the reinforcement effect of part of the three-mode redundancy on the device.

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