SRAM type FPGA test method based on irradiation test environment simulation

Abstract

The invention provides an SRAM type FPGA test method based on irradiation test environment simulation. Fault injection is performed on a circuit realized by adoption of an SRAM type FPGA, by continuous injection of single event upset faults of random addresses and random types into the circuit, influence of parameters of an incident particle LET value, fluence rate Flux and fluence Fluence on the circuit in a ground irradiation test is simulated, and effectiveness of circuit reinforcing design is quantitatively evaluated. The SRAM type FPGA test method provided by the invention can obtain a characteristic curve of changes of a dynamic upset section of the circuit with the LET value, thereby estimating an in-orbit failure rate.

Description

technical field [0001] The invention belongs to the field of aerospace, and relates to a SRAM type FPGA test method based on radiation test environment simulation. Background technique [0002] SRAM (Static Random Access Memory) FPGA (Field Programmable Gate Arrays) has received more and more attention and applications in the aerospace field due to its advantages of reprogrammable, short development cycle, and high integration. However, in the space environment, the single event effect (Single Event Effect, SEE) especially the single event upset (Single Event Upset, SEU) caused by the bombardment of high-energy particles seriously affects the reliability of aerospace devices. Therefore, the user design must be evaluated for reliability before application. [0003] For the design of SRAM FPGA, there are two commonly used reliability evaluation methods: ground radiation test and fault injection. The former uses accelerators to generate heavy ions, protons and neutrons with d...

AI Technical Summary

Problems solved by technology

[0009] (1) After the ground irradiation test, the device under test cannot be used due to damage, the cost is high, the test is difficult, and the test parameters are troublesome to adjust, which may cause radiation pollution and has a high risk

Moreover, it is difficult to apply for domestic irradiation testing machines, and the testing time is limited;

[0010] (2) Patent CN102540062A simulates the irradiation dose and irradiation time, but it cannot obtain the relationship curve between the dynamic flip section of the circuit design and the parameters such as the LET value of the incident particles, the fluence rate Flux, etc. like the irradiation test, and the reference value of the test results limited

Moreover, after the invention calculates the number M of bit flips, all faults are injected into the circuit design through only one partial reconstruction, which is inconsistent with the real irradiation test environment;

[0011] (3) The patent CN102540062A requires an additional method of unit random flipping to calculate the refresh cycle of the circuit design, and the operation is more complicated;

[0012] (4) Patent CN102540062A only considers single-bit upset (SBU) fault type, but as the feature size of the device decreases, a single particle incident may cause charge collection in multiple adjacent PN junctions, causing multi-bit upset (MBU) );

[0013] (5) Patent CN102540062A needs to use an additional method, which is specially used to obtain the refresh cycle, and the operation is relatively complicated and the efficiency is low

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