Error detecting and error correcting system for tiny satellite star load computer data storage

A technology for on-board computer and data storage, applied in the field of microsatellites and aerospace electronics

Inactive Publication Date: 2009-01-28
TSINGHUA UNIV
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  • Description
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Problems solved by technology

This requires a 3×16bit redundant memory space

Method used

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  • Error detecting and error correcting system for tiny satellite star load computer data storage
  • Error detecting and error correcting system for tiny satellite star load computer data storage
  • Error detecting and error correcting system for tiny satellite star load computer data storage

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Embodiment Construction

[0027] This system needs to cooperate with the central processor of the specific on-board computer to work together, and its interface needs to lead out the data bus line, address bus, and control bus of the processor. In order to have versatility, this system needs to lead out 16 data buses, 25 address buses, and 3 control buses of the external processor, in which the control lines are connected to the read and write status indication, read enable and write enable of the field programmable device, The mode selection control line is given as the high address line.

[0028]Inside the system, among the connections drawn from the external processor, the low address lines A0 to A17 are connected to the static memory in the system, and all other connections are connected to the field programmable devices in the system. The 16-bit data line Dinout (0~15) is expanded into Dinouta (0~15), Dinoutb (0~15), Dinoutc (0~15) 48 bits through the field programmable device, connected to the st...

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Abstract

An error detection and correction system for the data storage of a miniature satellite onboard spacecraft computer belongs to the technical field of the computer storage in a miniature satellite in the space technology. The system is characterized in that the system comprises a static memory storage unit assembly and a field programmable device FPGA, wherein the FPGA comprises a Hamming error correcting circuit, a triple modular redundancy decision circuit, two both-way tristate gates, an address logic circuit and a mode control circuit; according to the address contents of an external central processing unit, the mode control circuit selects any of the three modes of Hamming error correction, triple modular redundancy decision and error-free control; and according to the storage space configured by the address logic circuit controlled by the mode control circuit, the storage unit assembly consisting of 12 static memory storage units carries out the read-write operation of the data signal inputted by the central processing unit through the two both-way tristate gates. As the system respectively separates the memory space of the memory storage unit assembly into flexible and adjustable groups according to the three modes, the memory can be flexibly distributed according to the error correcting modes so as to be fully utilized.

Description

technical field [0001] The invention realizes an error detection and correction technology for a data storage system of a micro-satellite on-board computer aiming at the single-event effect generated in outer space, and belongs to the fields of Micro Satellite and Space Avionics. Background technique [0002] Radiation is one of the main problems faced by spacecraft in the space environment. Various high-energy particles in space (including high-energy protons, neutrons, alpha particles, heavy ions, etc.) have high kinetic energy, and may affect the logic state of semiconductor circuits when passing through, and even cause permanent damage to semiconductor materials. The impact of a single high-energy particle on the function of an electronic device is called a single event effect. Among them, special attention needs to be paid to the single event upset (SEU) problem that causes the stored content to change between '0' and '1'. [0003] The research and development ideas o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/10
Inventor 尤政田贺祥李滨于世洁宋丹
Owner TSINGHUA UNIV
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