Self-reconfigurable D/TMR (Dual/Triple Modular Redundancy) system based on FPGA (Field Programmable Gate Array) and fault-tolerant design method thereof

Abstract

The invention discloses a fault-tolerant design method of a self-reconfigurable D/TMR (Dual/Triple Modular Redundancy) system based on an FPGA (Field Programmable Gate Array), comprising the following work steps: (a) utilizing a DMR bit stream to configure a dynamic reconfigurable area; (b) detecting the state of a DMR system through a detection circuit and judging whether faults exit; if not, keeping a DMR state of the dynamic reconfigurable area; otherwise, reading a configuration TMR bit stream on a CF (Collaborative Filtering) card; and configuring the dynamic reconfigurable area into a TMR state. The fault-tolerant design method provided by the invention can overcome the disadvantages of a fault-tolerant mechanism, has the advantages of higher resource utilization rate, high fault-tolerant capability and high reliability, and can realize rapid self-repairing of faults. The invention further discloses the self-reconfigurable D/TMR system based on the FPGA.

Description

technical field [0001] The invention relates to a self-reconfiguration D / TMR system and a fault-tolerant design method thereof, belonging to the technical field of digital system fault tolerance. Background technique [0002] With the rapid development of science and technology, the pace of human exploration and development of space is accelerating, and the structures and functions of various space vehicles are becoming more and more complex, and the requirements for life and reliability are also getting higher and higher. However, due to the harsh electromagnetic interference and extreme temperature environment in which the spacecraft operates in space, it is easy to cause failures of on-board electronic equipment; in addition, the current electronic system is moving towards a complex and highly integrated system-on-chip SOC) direction, traditional electronic system redundancy backup (such as system-level, module-level, chip-level backup) fault-tolerant design methods are...

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Problems solved by technology

However, various faults may occur in FPGA logic circuits working in harsh environments, such as transient faults and permanent faults such as Single Event Upset (SEU) phenomena caused by space particle radiation

In recent years, researchers have begun to study FPGA on-chip redundant fault-tolerant technologies, such as FPGA on-chip N-mode redundancy, master-backup redundancy, etc. However, most of these fault-tolerant design methods still use traditional device backup redundancy schemes. The shortcomings of low resource utilization and weak system fault tolerance still exist. How to use the reconfigurable characteristics of FPGA to build a highly reliable fault-tolerant system and how to realize online repair of faulty modules in the fault-tolerant system are important research and exploration issues. Frontier topics

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