8 results about "Error-tolerant design" patented technology

The application discloses a fault-tolerant quantum architecture design method, device, storage medium and electronic equipment, wherein the fault-tolerant quantum architecture design method comprises the following steps: obtaining hardware configuration parameters of a target quantum computing architecture, and constructing a fault tree model based on the hardware configuration parameters; performing vulnerability evaluation on the fault tree model, generating a vulnerability quantification index, and determining a candidate component set requiring deployment of a resilience mechanism according to the vulnerability quantification index; configuring a corresponding resilience strategy for each component in the candidate component set, and generating a graceful degradation planning table based on the resilience strategy; inputting the fault tree model, the resilience strategy and the graceful degradation planning table into a formal verification engine to output a reliability certificate; and generating an authenticated resilience architecture netlist through a hardware description language according to the reliability certificate. The application can solve the technical problems that the quantum computing system lacks systematic fault-tolerant design, the fault response capability is insufficient, and the reliability index cannot be verified in the prior art.

This application discloses a method for testing and quantifying the anti-interference capability of a spiking neural network, belonging to the field of neuromorphic computing and artificial intelligence. The method includes: conducting multiple independent test experiments on a spiking neural network model to be deployed on a target hardware platform in a simulation environment to obtain a set of technical state signals corresponding to each test experiment; performing multi-dimensional quantitative analysis based on the first and second sets of technical state signals obtained from each test experiment to determine multiple performance indicators used to characterize the anti-interference capability of the spiking neural network model; normalizing and fusing the multiple performance indicators to generate a network anti-interference capability index; and using the network anti-interference capability index as a reliability pre-evaluation parameter of the spiking neural network model on the target hardware platform to guide the fault-tolerant design of the target hardware platform or to optimize the robustness of the spiking neural network model.

Methods and power conversion systems related to fault-tolerant operation for aircraft electric propulsion. The fault-tolerant system continues to operate in the event of a component failure, i.e., one or more faults within a component. The fault-tolerant design enables the system to continue its intended operation, possibly at a reduced level, when some parts of the system fail, rather than completely failing. When a turn-to-turn fault in an AC motor is detected, the motor controller shorts together three top switches or three bottom switches of the inverter, effectively shorting the associated stator winding, to divert the fault current from the motor winding to the motor controller, if cooling is available. Also, when a fault in the motor controller or at the input to the motor controller is detected, the motor controller cuts power to the motor by issuing a command to open the upstream contactor from the high voltage DC bus input.

The application provides a kind of high-precision photoelectric encoder measurement result high fault-tolerant design method and system on satellite, comprising: by radial transceiving light path double-channel design, obtain two-way absolute angle data and two-way incremental data, four-way measurement data output angle data according to predetermined judgment rule, judgment rule is suitable for single point failure to output correct data, when multiple faults occur, according to the specific situation analysis, the judgment rule can be avoided to avoid the fault state and change to obtain correct angle data output, realize automatic fault-tolerant design.

The application discloses a kind of coiler spring seat interference-proof fault-tolerant design, installation and monitoring method and coiler, and relates to the technical field of metallurgical equipment.The method includes three stages: in the fault-tolerant design stage, the key matching size of spring seat and jaw movement system is actively introduced with safety margin Δ, to tolerate abnormal working condition from the source;In the precise assembly verification stage, the "double limit position measurement method" is used to verify the assembly gap at the two endpoints of the expansion and contraction diameter in the field, to ensure no interference;In the preventive monitoring stage, the above gap is measured regularly and compared with the preset threshold, to realize predictive maintenance.The application solves the technical problem of spring seat fatigue fracture caused by low design gap fault tolerance and easy movement interference under abnormal working condition through the above systematic method, significantly improves the operation reliability and maintenance economy of the coiler.

This invention discloses an ECC fault-tolerant structure and memory fault-tolerant design method covering the entire communication path, relating to the field of on-chip memory technology. It addresses the technical problem that existing on-chip memory EDAC technology's protection scope is limited to the on-chip memory cell itself, and introduces additional errors during data transmission, making it difficult to guarantee data integrity. The ECC fault-tolerant structure covering the entire communication path includes a host module, an interconnect bus, and storage components. The host module is configured with an ECC codec. The host module is used to implement access control of the storage components. The interconnect bus is used to implement access routing between the host module and the storage components and establish a connection between them. The host module initiates a data write access, encodes the pre-written data using ECC, and then initiates a write access to the storage component. The interconnect bus routes the access to the corresponding storage component based on the access address.

The application discloses an EHD printing integrated high-precision FPC antenna and a preparation method, and belongs to the technical field of FPC antennas, and comprises a substrate and a koch snowflake fractal radiation patch formed on the substrate; the metal line of the koch snowflake fractal radiation patch has an optimized nominal width W opt , and W opt is a parameter determined after a collaborative fault-tolerant design of the antenna structure, by modeling the line width manufacturing error of the EHD printing as a random variable within the range of ±15μm and taking the resonance frequency offset of the antenna not greater than 1.5% as an optimization target; the radiation patch is formed after being printed by conductive ink and undergoing synchronous ultraviolet pre-curing and stepwise thermal curing, and the conductive ink contains a load type Ag2O-MXene composite powder; through deep synergy and optimization of the structure fault-tolerant design, special functional materials and precise manufacturing processes, the application solves the mismatch problem in the process from a high-performance design model to high-fidelity physical antenna manufacturing, and especially provides a reliable integrated solution for flexible electronic manufacturing of complex micro-patterns.

This invention relates to the field of branch target buffer fault-tolerant design, and proposes a fault-tolerant design system and method based on a fully connected L0 BTB, comprising: XORing the current instruction address to obtain the XOR checksum of the current instruction address; concatenating the current instruction address and the XOR checksum and writing them simultaneously into two L0 BTBs; accessing both L0 BTBs simultaneously with the current instruction address, and comparing the current instruction address with the target instruction address to determine whether an L0 BTB is hit; if one of the L0 BTBs is hit, setting the enable signal value to 1, obtaining the content of the entry and performing an XOR check on the entry; if the XOR checksum of the entry is the same as the checksum stored in the entry, then the entry is taken as a candidate entry; making a decision based on the obtained candidate entries; if the check result shows that no candidate entry appears, then it is considered that the current instruction address has not hit an L0 BTB.