A register single event effect analog simulation method for an aerospace chip

A single event effect and simulation technology, applied in design optimization/simulation, instruments, special data processing applications, etc., can solve problems such as single event effect fault injection in space application chips, achieve high authenticity and reliability, and improve efficiency , the effect of improving flexibility

Active Publication Date: 2019-04-02
BEIJING INST OF CONTROL ENG
View PDF5 Cites 5 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is: to overcome the deficiencies of the prior art, the present invention provides a register single event effect simulation method for aerospace chips, to solve the problem of space application

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A register single event effect analog simulation method for an aerospace chip
  • A register single event effect analog simulation method for an aerospace chip
  • A register single event effect analog simulation method for an aerospace chip

Examples

Experimental program
Comparison scheme
Effect test

Embodiment

[0041] A detailed explanation of a register single event effect simulation method for aerospace chips combined with a specific implementation case (SapceWire protocol chip):

[0042] 1) Based on the SIMC 0.13um process library file, use the Design Compiler tool to design the RTL of the SapceWire protocol chip (hereinafter referred to as the SPW chip) to obtain the gate-level netlist of the SPW chip;

[0043] 2) Based on the data sheet of the SIMC 0.13um process library, the types of all registers of SIMC 0.13um and the definitions of input and output ports are obtained (there are many types of registers, and 2 types of them are listed):

[0044]

[0045] 3) Based on the data manual of the SIMC 0.13um process unit library file, all register types under the process are obtained, and the number of registers used in the SPW chip netlist obtained in step 1) is 138907; and the types used are only Contains DFFSHQX1, DFFSHQX2, DFFSHQX4, DFFSHQX8. There are many register lists, onl...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention discloses a register single event effect analog simulation method for an aerospace chip. The method comprises the steps of constructing a parameterized register fault simulation model; randomly replacing the normal register simulation model in the chip netlist with a register fault simulation model, wherein the replacement number is determined by the error turnover rate of the spacenavigation chip set in the space environment and the total number of registers in the chip, the error occurrence time of the registers is randomly selected from 0 to the maximum simulation time, simulating the simulation fault module behavior through a simulation tool, and then verifying the effectiveness of the chip-level register fault-tolerant strategy. According to the method, the single eventeffect soft error can be simulated and the hard error formed by the high-energy single event effect can be simulated without analyzing codes and independently designing a test case. The method can support the aerospace radiation reinforcement research and can be applied to verification and analysis of fault-tolerant design of the single event effect fault.

Description

technical field [0001] The invention relates to a register single event effect simulation method, which belongs to the technical field of verification of anti-irradiation chips. Background technique [0002] In the space environment, high-energy particles pass through semiconductor materials, and consume energy by releasing electron-hole pairs on the trajectory of the particles. When the energy is released, the particles will stop. Charges accumulate and flow within the track, and parasitic devices or weak links are activated, resulting in various types of damage, which can be divided into: hard errors and soft errors. Hard errors are manifested as permanent damage to the device itself, while soft errors are manifested as flipping of the logic state of the circuit and random changes in stored data, and the device itself is not damaged. Hard errors require the incident particles to have extremely high energy, and the flux of high-energy particles is less than that of low-ene...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
IPC IPC(8): G06F17/50
CPCG06F30/20
Inventor 高瑛珂梁贤赓刘奇周丽艳刘鸿瑾刘波于广良华更新
Owner BEIJING INST OF CONTROL ENG
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products