SEU fault tolerance technology applied to FPGA

A fault-tolerant technology and a fault-based technology, applied in the direction of error detection/correction, instrumentation, electrical digital data processing, etc., can solve problems such as system failure, wrong data information, etc., to reduce hardware scale, improve reliability, and reduce the scope of reconstruction Effect

Inactive Publication Date: 2017-03-01
汪鹏
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Problems solved by technology

[0007] If one bit of the configuration data changes, that is, from "0" state to "1" state, or from "1" state to "0" state, then the corresponding circuit will change the original behavior and implement non-user settings The operation, this effect will eventually be transmitted to the output of the device, causing the user to get unexpected results, or get wrong data information, causing the system to fail

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  • SEU fault tolerance technology applied to FPGA
  • SEU fault tolerance technology applied to FPGA
  • SEU fault tolerance technology applied to FPGA

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Embodiment Construction

[0015] The present invention will be described in detail below in conjunction with the accompanying drawings.

[0016] figure 1 Shown is the structure of the bottom layer of SRAM FPGA. The leftmost dashed box in the figure is the CLB programmable logic block. For Virtex-5 series FPGAs, each CLB consists of two Slices, and each Slice contains 4 LUTs and 4 flip-flops. According to the user's design, the CLB can be configured as the corresponding combinatorial logic or sequential logic, and it can also be configured as distributed RAM or distributed ROM for use. The LUT in the CLB is mainly used to realize the combinatorial logic, and the trigger is mainly used for It is used to realize the intermediate results of sequential logic and storage circuit operation. BRAM is an on-chip storage resource used to implement various storage functions and improve the overall operating efficiency of the FPGA. M is a configuration memory unit, which is used to store configuration data of th...

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Abstract

The invention discloses an SEU fault tolerance design applied to an FPGA. An idea of a reconfigurable technology is used for SEU fault tolerance in the FPGA to improve the operation reliability of a system. Switching of a logic function is achieved by a reconfigurable region A through dynamically loading a configuration file A1.bit or A2.bit.

Description

technical field [0001] The invention relates to a FPGA SEU fault tolerance technology, which is especially suitable for the dynamic reconfigurable technology of FPGA. Background technique [0002] Because there are a large number of complex high-energy particles in the space environment, they run randomly and randomly, and it is inevitable that they will collide with semiconductor devices in aerospace equipment. When these high-energy particles hit the sensitive area in the device, the logical connection relationship in the device will be changed accordingly, thereby changing the function of the device. The configuration storage unit in the SRAM FPGA is very sensitive to the single event effect, and it is very easy to flip the configuration bit due to the radiation of high-energy particles, that is, the single event flip SEU, and the content of the FPGA configuration memory determines the top-level circuit structure of the FPGA. The functions of the FPGA are closely related...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/00
Inventor 汪鹏
Owner 汪鹏
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